Wen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a fin structure over a semiconductor substrate and forming a gate stack over the fin structure. The method also includes forming an epitaxial structure over the fin structure, and the epitaxial structure is adjacent to the gate stack. The method further includes forming a dielectric layer over the epitaxial structure and forming an opening in the dielectric layer to expose the epitaxial structure. In addition, the method includes applying a metal-containing material on the epitaxial structure while the epitaxial structure is heated so that a portion of the epitaxial structure is transformed to form a metal-semiconductor compound region.
Abstract: A mobile device includes a host upper cover, a host lower cover, a metal cavity structure, a protruding radiation element, a nonconductive connection element, and a feeding element. The metal cavity structure is coupled between the host upper cover and the host lower cover. The metal cavity structure includes a first metal partition and a second metal partition. The first metal partition has an opening. The nonconductive connection element is connected to the edge of the opening of the first metal partition. The nonconductive connection element is configured to support and surround the protruding radiation element. The feeding element is coupled to a signal source and is disposed adjacent to the protruding radiation element. An antenna structure is formed by the feeding element and the protruding radiation element.
Abstract: A method for calculating glomerular filtration rate (GFR) is revealed. A circumference of a patent's neck is measured and then is substituted into an exponential formula together with clinical factors and patient's age for estimating GFR. The present method has a better performance compared with methods for evaluating renal function by GFR available now. The methods available now have poor performance in prediction of loss of renal function at early stage. Some patients are diagnosed at an advanced stage so that they miss the opportunity of early treatment.
Abstract: An eye diagram measurement device includes a first mapping circuitry, a count circuitry, a second mapping circuitry and a memory circuitry. The first mapping circuitry maps one of plurality of internal signals of an electronic device to a first data signal having a predetermined number of bits. The counter circuitry performs a counting operation according to the first data signal and a plurality of signal values associated with the predetermined number of bits, to generate a plurality of count signals. The second mapping circuitry maps the count signals respectively to a plurality of eye diagram measurement signals corresponding to a present phase. The memory circuitry stores the eye diagram measurement signals in order to provide the eye diagram measurement signals to an external system for generating an eye diagram measurement result of the electronic device.
May 10, 2019
January 9, 2020
Wen-Juh KANG, Yu-Chu CHEN, Hsun-Wei KAO
Abstract: Structures and formation methods of a semiconductor device structure are provided. A semiconductor device structure includes a first dielectric layer and a second dielectric layer over a semiconductor substrate. A cavity penetrates through the first dielectric layer and the second dielectric layer. The semiconductor device structure also includes a first movable membrane between the first dielectric layer and the second dielectric layer. The first movable membrane is partially exposed through the cavity. The first movable membrane includes first corrugated portions arranged along an edge of the cavity.
Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.
Abstract: A method for forming a semiconductor device structure is provided. The method includes disposing a semiconductor substrate in a physical vapor deposition (PVD) chamber. The method also includes introducing a plasma-forming gas into the PVD chamber, and the plasma-forming gas contains an oxygen-containing gas. The method further includes applying a radio frequency (RF) power to a metal target in the PVD chamber to excite the plasma-forming gas to generate plasma. In addition, the method includes directing the plasma towards the metal target positioned in the PVD chamber such that an etch stop layer is formed over the semiconductor substrate.
Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.
Abstract: A method embodiment includes providing a MEMS wafer. A portion of the MEMS wafer is patterned to provide a first membrane for a microphone device and a second membrane for a pressure sensor device. A carrier wafer is bonded to the MEMS wafer. The carrier wafer is etched to expose the first membrane and a first surface of the second membrane to an ambient environment. A MEMS structure is formed in the MEMS wafer. A cap wafer is bonded to a side of the MEMS wafer opposing the carrier wafer to form a first sealed cavity including the MEMS structure and a second sealed cavity including a second surface of the second membrane for the pressure sensor device. The cap wafer comprises an interconnect structure. A through-via electrically connected to the interconnect structure is formed in the cap wafer.
Abstract: A MEMS microphone includes a backplate that has a plurality of open areas, and a diaphragm spaced apart from the backplate. The diaphragm is deformable by sound waves to cause gaps between the backplate and the diaphragm being changed at multiple locations on the diaphragm. The diaphragm includes a plurality of anchor areas, located near a boundary of the diaphragm, which is fixed relative to the backplate. The diaphragm also includes multiple vent valves. Examples of the vent valve include a wing vent valve and a vortex vent valve.
June 25, 2018
December 26, 2019
Chun-Wen Cheng, Chia-Hua Chu, Chun Yin Tsai
Abstract: Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.
Abstract: A method embodiment includes providing a micro-electromechanical (MEMS) wafer including a polysilicon layer having a first and a second portion. A carrier wafer is bonded to a first surface of the MEMS wafer. Bonding the carrier wafer creates a first cavity. A first surface of the first portion of the polysilicon layer is exposed to a pressure level of the first cavity. A cap wafer is bonded to a second surface of the MEMS wafer opposite the first surface of the MEMS wafer. The bonding the cap wafer creates a second cavity comprising the second portion of the polysilicon layer and a third cavity. A second surface of the first portion of the polysilicon layer is exposed to a pressure level of the third cavity. The first cavity or the third cavity is exposed to an ambient environment.
Abstract: Some embodiments of the present disclosure provide a gas sensor in an IOT. The gas sensor includes a substrate, a conductor disposed above the substrate, and a sensing film disposed over the conductor. The conductor has a top-view pattern including a plurality of openings, a minimal dimension of the opening being less than about 4 micrometer; and a perimeter enclosing the opening. Some embodiments of the present disclosure provide a method of manufacturing a gas sensor. The method includes receiving a substrate; forming a conductor, over the substrate; patterning the conductor to form a plurality of openings in the conductor by an etching operation, and forming a gas-sensing film over the conductor. The openings are arranged in a repeating pattern, and a minimal dimension of the opening being about 4 micrometer.
October 8, 2015
Date of Patent:
December 17, 2019
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: An actuator is provided, including a fixed assembly and a movable assembly. The fixed assembly includes a coil module, a base, a first screwing member, and a linear rail. The first screwing member passes through the base and the linear rail, and the linear rail is positioned on the base. The movable assembly includes a U-shaped back board having an inner space, a first magnetic module, a second magnetic module aligned with the first magnetic module, and a sliding block. The first and second magnetic modules are disposed on the U-shaped back board and accommodated in the inner space. The coil module is disposed between the first magnetic module and the second magnetic module. The sliding block is positioned on the U-shaped back board in the inner space, and slidably connected to the linear rail.
Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a memory region and a periphery region; forming a first trench and a second trench in substrate on the memory region, wherein a width of the second trench is greater than a width of the first trench; forming a first liner in the first trench and the second trench; forming a second liner on the first liner, wherein the second liner completely fills the first trench and partly fills the second trench; and planarizing the second liner and the first liner to form a first isolation structure and a second isolation structure.
Abstract: The present disclosure, in some embodiments, relates to a resistive random access memory (RRAM) cell. The RRAM cell has a bottom electrode over a substrate. A data storage layer is over the bottom electrode and has a first thickness. A capping layer is over the data storage layer. The capping layer has a second thickness that is in a range of between approximately 1.9 and approximately 3 times thicker than the first thickness. A top electrode is over the capping layer.
Abstract: The present disclosure provides a CMOS MEMS device. The CMOS MEMS device includes a first substrate, a second substrate, a first polysilicon and a second polysilicon. The second substrate includes a movable part and is located over the first substrate. The first polysilicon penetrates the second substrate and is adjacent to a first side of the movable part of the second substrate. The second polysilicon penetrates the second substrate and is adjacent to a second side of the movable part of the second substrate.
September 22, 2015
Date of Patent:
December 3, 2019
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
Abstract: An energy regulation circuit is provided. A first voltage regulator adjusts an input voltage to generate an adjustment voltage. A first energy storage is charged according to the input voltage or the adjustment voltage. A first switch is coupled to the first energy storage. A second energy storage is coupled to the first switch. When the first switch is turned on, the second energy storage is coupled to the first energy storage in parallel. When the first switch is turned off, a second voltage regulator generates an operation voltage according to the voltage stored in the first energy storage. When the first switch is turned on, the second voltage regulator generates the operation voltage according to the voltages stored in the first and second energy storages. A controller operates according to the operation voltage.
Abstract: A mobile device includes a host upper cover, a host lower cover, a metal cavity structure, an H-shaped slot antenna, and a feeding element. The metal cavity structure is coupled between the host upper cover and the host lower cover. The H-shaped slot antenna is formed on the host upper cover, the host lower cover, the metal cavity structure, the host upper cover and the metal cavity structure, or the host lower cover and the metal cavity structure. The feeding element is coupled to a signal source. The feeding element is configured to excite the H-shaped slot antenna.
Abstract: A semiconductor device includes a semiconductor substrate, a gate dielectric, a gate electrode and a pair of source/drain regions. The gate dielectric is disposed in the semiconductor substrate having a concave profile that defines an upper boundary lower than an upper surface of the semiconductor substrate. The gate electrode is disposed over the gate dielectric. The pair of source/drain regions are disposed on opposing sides of the gate dielectric.