Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: A rapid detection method of sulfide content is provided, which includes determining the concentration and volume of a metal ion solution, the volume of a sample, and the amount of a chemical reducing agent, depending on a threshold value. It also provides preparing the metal ion solution, sampling the sample, and mixing the metal ion solution with the sample to result in a mixture solution. The chemical reducing agent is added into the mixture solution to obtain the resulting solution. Naked-eye observation of the resulting solution is used to determine whether the sulfide content of the sample is over the threshold value. When the resulting solution is clear, this indicates that the sulfide content of the sample is greater than or equal to the threshold value. When the resulting solution contains precipitates, this indicates that the sulfide content of the sample is lower than the threshold value.

Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.

Abstract: A method for eliminating a ring effect is provided. The method includes: capturing, by a camera, a standard ring image generated by light illuminating a standard Fresnel lens; establishing a compensation lookup table according to the standard ring image and obtaining a standard ring center point; capturing, by the camera, a ring image generated by the light illuminating a Fresnel lens to be tested; obtaining a ring center point according to the ring image; obtaining a conversion relationship between the ring center point and the standard ring center point; and performing a compensation procedure on the ring image according to the compensation lookup table and the conversion relationship to eliminate the ring effect in the ring image.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: A connector assembly with latching provided by a rotating latch bar. The connector has a low height, with the rotating latch bar providing secure engagement between mated connectors of the connector assembly. The latch bar may be shaped to provide spring force that urges the mated connectors together. The connector assembly may be formed with a cable connector and a board connector. The low height of the board connector enables the connector to be mounted close to high speed electronic components, such as a processor, even if covered by a heat sink, as the connector may fit under the heat sink. The cable connector may be coupled, via a cable, to an I/O connector or other component remote from the high speed electronic component.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.

Abstract: A semiconductor integrated circuit comprises a semiconductor substrate having a via-hole, a front-side-metal layer formed on a top surface of the semiconductor substrate, a seed-metal layer and a backside-metal layer. A bottom surface of an inner surface of the via-hole is at least partially defined by the front-side-metal layer. A surrounding surface of the inner surface of the via-hole is at least partially defined by the semiconductor substrate. The seed-metal layer is formed on the inner surface of the via-hole and a bottom surface of the semiconductor substrate such that the seed-metal layer and the front-side-metal layer are connected. The backside-metal layer is formed on an outer surface of the seed-metal layer. An aspect ratio of the via-hole is greater than or equal to 0.2 and less than or equal to 3, thereby a thickness uniformity of the backside-metal layer is improved.

Abstract: The disclosure relates to a heat dissipation module, a display device having the same, and an assembly method thereof. Place the heat dissipation structure in between the chip of the COF (chip-on-film) and the thermal-conductive supporting component, heat generated by the chip of the COF can be absorbed by the heat dissipation structure and then be transferred to the thermal-conductive supporting component through the heat dissipation structure. As a result, the temperature of the chip is decreased, and the chip is avoided from operating at high temperature to deteriorate its performance and to result in thermal deformation or any other negative effects on the nearby components.

Abstract: The present disclosure describes a method to form silicon germanium (SiGe) source/drain regions with the incorporation of a lateral etch in the epitaxial source/drain growth process. For example, the method can include forming a plurality of fins on a substrate, where each of the plurality of fins has a first width. The SiGe source/drain regions can be formed on the plurality of fins, where each SiGe source/drain region has a second width in a common direction with the first width and a height. The method can also include selectively etching—e.g., via a lateral etch—the SiGe source/drain regions to decrease the second width of the SiGe source/drain regions. By decreasing the width of the SiGe source/drain regions, electrical shorts between neighboring fins can be prevented or minimized. Further, the method can include growing an epitaxial capping layer over the Si/Ge source/drain regions.

Abstract: A mobile device holding device comprises a basement including an inner accommodation space; a document feeding path including a scanning area, the document feeding path being disposed in said accommodation space; an input tray disposed on an upstream of the document feeding path to accommodate documents to be scanned; an output tray disposed on a downstream of the document feeding path to eject scanned documents; a document feeding unit disposed in the accommodation space for transmitting documents through the document feeding path; and a device holder disposed on the basement to fix a mobile device; wherein the device holder is moved to align the mobile device with the scanning area for capturing the image within the scanning area, and ensuring that the shooting area of the mobile device is not less than the width of documents to be scanned.

Abstract: A high-speed flat cable having a better bending/folding memory and a manufacturing method thereof are provided. The high-speed flat cable includes a plurality of shielded signal units, one or more bendable composite layers, and an adhesive layer. The shielded signal units are substantially coplanar, spaced apart from each other or adjoining each other. The one or more bendable composite layers includes an inner insulating film layer, a bendable aluminum foil layer, and an outer insulating film layer. The one or more bendable composite layers composed of the inner insulating film layer, the bendable aluminum foil layer, and the outer insulating film layer increase its mechanical bending/folding property to improve the bending/folding memory. The one or more bendable composite layers allow the flat cable to be bent with ease without rebounding, thereby enhancing production efficiency.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: The disclosure relates to a heat dissipation module, a display device having the same, and an assembly method thereof. Place the heat dissipation structure in between the chip of the COF (chip-on-film) and the thermal-conductive supporting component, heat generated by the chip of the COF can be absorbed by the heat dissipation structure and then be transferred to the thermal-conductive supporting component through the heat dissipation structure. As a result, the temperature of the chip is decreased, and the chip is avoided from operating at high temperature to deteriorate its performance and to result in thermal deformation or any other negative effects on the nearby components.

Abstract: Techniques for a resource management advice service are provided. In some examples, resource management advice and/or instructions may be provided for use with mobile devices, mobile applications, cloud applications, and/or other web-based applications. For example a mobile client may request to perform one or more resource management operations associated with a service provider. Based at least in part on the requested operation and/or the particular service provider, advice and/or instructions for managing the resource may be provided.

Abstract: A connector assembly configured for compact, high speed electronic systems. The assembly includes a board connector and a cable connector that may be mated by moving the cable connector in a mating direction perpendicular to a printed circuit board to which the board connector is mounted. The cable and board connectors may latch when mated and may be unlatched and unmated by pulling on a tab at a top of the cable connector in a direction opposite the mating direction. As a result, little clearance is required around the board connector to access the latching components. Such a connector may enable an electronic device with high signal integrity because the connector can be mounted close to an electronic component that processes high speed signals, providing a short, and high integrity signal paths for high speed signals.

Abstract: A connector assembly with latching provided by a rotating latch bar. The connector has a low height, with the rotating latch bar providing secure engagement between mated connectors of the connector assembly. The latch bar may be shaped to provide spring force that urges the mated connectors together. The connector assembly may be formed with a cable connector and a board connector. The low height of the board connector enables the connector to be mounted close to high speed electronic components, such as a processor, even if covered by a heat sink, as the connector may fit under the heat sink. The cable connector may be coupled, via a cable, to an I/O connector or other component remote from the high speed electronic component.

Abstract: Systems, apparatus, and methods are described for robotic learning and execution of skills. A robotic apparatus can include a memory, a processor, sensors, and one or more movable components (e.g., a manipulating element and/or a transport element). The processor can be operatively coupled to the memory, the movable elements, and the sensors, and configured to obtain information of an environment, including one or more objects located within the environment. In some embodiments, the processor can be configured to learn skills through demonstration, exploration, user inputs, etc. In some embodiments, the processor can be configured to execute skills and/or arbitrate between different behaviors and/or actions. In some embodiments, the processor can be configured to learn an environmental constraint. In some embodiments, the processor can be configured to learn using a general model of a skill.