Patents by Inventor Wen Chu

Wen Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200076126
    Abstract: A connector assembly with latching provided by a rotating latch bar. The connector has a low height, with the rotating latch bar providing secure engagement between mated connectors of the connector assembly. The latch bar may be shaped to provide spring force that urges the mated connectors together. The connector assembly may be formed with a cable connector and a board connector. The low height of the board connector enables the connector to be mounted close to high speed electronic components, such as a processor, even if covered by a heat sink, as the connector may fit under the heat sink. The cable connector may be coupled, via a cable, to an I/O connector or other component remote from the high speed electronic component.
    Type: Application
    Filed: March 12, 2019
    Publication date: March 5, 2020
    Applicants: Amphenol AssembleTech (Xiamen) Co., Ltd, Amphenol East Asia Ltd.
    Inventors: Wen Chu Yang, Hang Li, Shujian Wang, Hui Tang, Zhenxing Liu, Xiyin Zhou, Wende Xu, Lo-Wen Lu
  • Publication number: 20200070343
    Abstract: Systems, apparatus, and methods are described for robotic learning and execution of skills. A robotic apparatus can include a memory, a processor, sensors, and one or more movable components (e.g., a manipulating element and/or a transport element). The processor can be operatively coupled to the memory, the movable elements, and the sensors, and configured to obtain information of an environment, including one or more objects located within the environment. In some embodiments, the processor can be configured to learn skills through demonstration, exploration, user inputs, etc. In some embodiments, the processor can be configured to execute skills and/or arbitrate between different behaviors and/or actions. In some embodiments, the processor can be configured to learn an environmental constraint. In some embodiments, the processor can be configured to learn using a general model of a skill.
    Type: Application
    Filed: June 28, 2019
    Publication date: March 5, 2020
    Inventors: Andrea Lockerd THOMAZ, Vivian Yaw-Wen Chu
  • Patent number: 10562820
    Abstract: A low-temperature co-fired microwave dielectric ceramic material includes: (a) 85 wt % to 99 wt % ceramic material comprising Mg2SiO4, Ca2SiO4, CaTiO3, and CaZrO3, wherein a weight ratio of Mg2SiO4 relative to Ca2SiO4 is of (1?x):x, a weight ratio of CaTiO3 relative to CaZrO3 is of y:z, and a weight ratio of entities of Mg2SiO4 and Ca2SiO4 relative to CaTiO3 is of (1?y?z):y, 0.2?x?0.7, 0.05?y?0.2, 0.05?z?0.4; and (b) 1 wt % to 15 wt % glass material composed of Li2O, BaO, SrO, CaO, B2O3, and SiO2.
    Type: Grant
    Filed: October 11, 2018
    Date of Patent: February 18, 2020
    Assignee: WALSIN TECHNOLOGY CORPORATION
    Inventors: Li-Wen Chu, Kuei-Chih Feng, Chih-Hao Liang
  • Publication number: 20200006530
    Abstract: In an embodiment, a device includes: a substrate; a first semiconductor layer extending from the substrate, the first semiconductor layer including silicon; a second semiconductor layer on the first semiconductor layer, the second semiconductor layer including silicon germanium, edge portions of the second semiconductor layer having a first germanium concentration, a center portion of the second semiconductor layer having a second germanium concentration, the second germanium concentration being less than the first germanium concentration, the edge portions of the second semiconductor layer including sides and a top surface of the second semiconductor layer; a gate stack on the second semiconductor layer; lightly doped source/drain regions in the second semiconductor layer, the lightly doped source/drain regions being adjacent the gate stack; and source and drain regions extending into the lightly doped source/drain regions.
    Type: Application
    Filed: April 1, 2019
    Publication date: January 2, 2020
    Inventors: Che-Yu Lin, Chien-Hung Chen, Wen-Chu Hsiao
  • Patent number: 10496147
    Abstract: An energy regulation circuit is provided. A first voltage regulator adjusts an input voltage to generate an adjustment voltage. A first energy storage is charged according to the input voltage or the adjustment voltage. A first switch is coupled to the first energy storage. A second energy storage is coupled to the first switch. When the first switch is turned on, the second energy storage is coupled to the first energy storage in parallel. When the first switch is turned off, a second voltage regulator generates an operation voltage according to the voltage stored in the first energy storage. When the first switch is turned on, the second voltage regulator generates the operation voltage according to the voltages stored in the first and second energy storages. A controller operates according to the operation voltage.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: December 3, 2019
    Assignee: VIA TECHNOLOGIES, INC.
    Inventors: Tze-Shiang Wang, Chih-Wen Chu
  • Patent number: 10426602
    Abstract: The present invention provides a device and method for inserting an IOL into an eye of a patient. The IOL injector is configured to automatically load an IOL into the injector by folding and aligning the IOL into a lens cartridge of the injector without manual manipulation of the IOL by the physician during the procedure. The injector is configured to properly orient and align the IOL within the injector and maintain proper alignment throughout delivery of the IOL to the eye of a patient and thereby ensuring that the IOL is properly positioned and oriented at a predetermined location in the eye.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: October 1, 2019
    Assignee: AST Products, Inc.
    Inventors: Wen-Chu Tseng, Ming-Yen Shen, William Lee
  • Publication number: 20190280115
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Kun-Mu LI, Liang-Yi CHEN, Wen-Chu HSIAO
  • Patent number: 10410979
    Abstract: An improved structure for reducing compound semiconductor wafer distortion comprises a contact metal layer and at least one stress balance layer. The contact metal layer is formed on a bottom surface of a compound semiconductor wafer; the at least one stress balance layer is formed on a bottom surface of the contact metal layer, wherein a thermal conductivity of the at least one stress balance layer is greater than or equal to 10 W/m-K. The stress suffered by the compound semiconductor wafer is balanced by the at least one stress balance layer, so that the distortion of the compound semiconductor wafer is reduced.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 10, 2019
    Assignee: WIN SEMICONDUCTORS CORP.
    Inventors: Chang-Hwang Hua, Wen Chu
  • Publication number: 20190259847
    Abstract: Semiconductor device structures and methods for forming the same are provided. A semiconductor device structure includes a gate structure over a semiconductor substrate. The gate structure includes a gate electrode layer and a gate dielectric layer covering a bottom surface and sidewalls of the gate electrode layer. The semiconductor device structure also includes spacer elements in contact with sidewalls of the gate structure and protruding from a top surface of the gate electrode layer. The semiconductor device structure also includes a first protection layer over the gate electrode layer and between the spacer elements. The semiconductor device structure also includes a dielectric layer over the first protection layer and between the spacer elements. A portion of the dielectric layer is between sidewalls of the spacer elements and sidewalls of the first protection layer.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 22, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Wen HUANG, Yun-Wen CHU, Hong-Hsien KE, Chia-Hui LIN, Shin-Yeu TSAI, Shih-Chieh CHANG
  • Publication number: 20190251246
    Abstract: Techniques for a resource management advice service are provided. In some examples, resource management advice and/or instructions may be provided for use with mobile devices, mobile applications, cloud applications, and/or other web-based applications. For example a mobile client may request to perform one or more resource management operations associated with a service provider. Based at least in part on the requested operation and/or the particular service provider, advice and/or instructions for managing the resource may be provided.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Applicant: Oracle International Corporation
    Inventors: Ajay Sondhi, Ching-Wen Chu, Beomsuk Kim
  • Publication number: 20190252369
    Abstract: An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.
    Type: Application
    Filed: May 10, 2018
    Publication date: August 15, 2019
    Applicant: Maxchip Electronics Corp.
    Inventors: Ruei-Siang Syu, Wen-Chu Lo, Chih-Feng Lin
  • Patent number: 10361187
    Abstract: An electrostatic discharge (ESD) protection device including a silicon controlled rectifier and a diode string arranged along a first direction is provided. The silicon controlled rectifier includes an anode and a cathode disposed separately from each other. The anode and the cathode respectively include doped regions. The doped regions in the anode are arranged along a second direction. The doped regions in the cathode are arranged along the second direction. The first direction intersects the second direction.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: July 23, 2019
    Assignee: Powerchip Semiconductor Manufacturing Corporation
    Inventors: Ruei-Siang Syu, Wen-Chu Lo, Chih-Feng Lin
  • Patent number: 10325089
    Abstract: Techniques for a resource management advice service are provided. In some examples, resource management advice and/or instructions may be provided for use with mobile devices, mobile applications, cloud applications, and/or other web-based applications. For example a mobile client may request to perform one or more resource management operations associated with a service provider. Based at least in part on the requested operation and/or the particular service provider, advice and/or instructions for managing the resource may be provided.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Oracle International Corporation
    Inventors: Ajay Sondhi, Ching-Wen Chu, Beomsuk Kim
  • Patent number: 10297690
    Abstract: A semiconductor device includes a gate structure formed over a channel region of the semiconductor device, a source/drain region adjacent the channel region, and an electrically conductive contact layer over the source/drain region. The source/drain region includes a first epitaxial layer having a first material composition and a second epitaxial layer formed over the first epitaxial layer. The second epitaxial layer has a second material composition different from the first composition. The electrically conductive contact layer is in contact with the first and second epitaxial layers. A bottom of the electrically conductive contact layer is located below an uppermost portion of the first epitaxial layer.
    Type: Grant
    Filed: October 4, 2017
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Liang-Yi Chen, Wen-Chu Hsiao
  • Patent number: 10276677
    Abstract: Semiconductor device structures and methods for forming the same are provided. A method for forming a semiconductor device structure includes forming a gate structure over a semiconductor substrate. The method also includes forming spacer elements adjoining sidewalls of the gate structure. The method further includes forming a protection material layer over the gate structure. The formation of the protection material layer includes a substantial non-plasma process. In addition, the method includes depositing a dielectric material layer over the protection material layer. The deposition of the dielectric material layer includes a plasma-involved process.
    Type: Grant
    Filed: April 21, 2017
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wen Huang, Yun-Wen Chu, Hong-Hsien Ke, Chia-Hui Lin, Shin-Yeu Tsai, Shih-Chieh Chang
  • Patent number: 10269648
    Abstract: Methods of fabricating a semiconductor device structure are provided. The method includes forming a fin structure over a substrate. The method also includes forming a gate structure over the fin structure. The method further includes epitaxially growing a source/drain structure covering the fin structure. In addition, the method includes epitaxially growing a capping layer over the source/drain structure. The capping layer has a top portion and a lower portion under the top portion. The top portion has a first thickness and the lower portion has a second. A ratio of the first thickness to the second thickness is in a range of about 1.01 to about 2. The method also includes etching the top portion and the lower portion of the capping layer. The method further includes forming a silicide layer over the source/drain structure and a contact over the silicide layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kun-Mu Li, Chih-Chiang Chang, Wen-Chu Hsiao
  • Publication number: 20190105151
    Abstract: The present invention provides a device and method for inserting an IOL into an eye of a patient. The IOL injector is configured to automatically load an IOL into the injector by folding and aligning the IOL into a lens cartridge of the injector without manual manipulation of the IOL by the physician during the procedure. The injector is configured to properly orient and align the IOL within the injector and maintain proper alignment throughout delivery of the IOL to the eye of a patient and thereby ensuring that the IOL is properly positioned and oriented at a predetermined location in the eye.
    Type: Application
    Filed: October 5, 2017
    Publication date: April 11, 2019
    Inventors: Wen-Chu Tseng, Ming-Yen Shen, William Lee
  • Publication number: 20190097006
    Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a gate structure, a first source/drain structure, and a contact structure. The gate structure has a gate dielectric layer over a first fin structure. The first source/drain structure is positioned in the first fin structure and adjacent to the gate structure. The first source/drain structure includes a first epitaxial layer in contact with the top surface of the first fin structure and a second epitaxial layer over the first epitaxial layer and extending above a bottom surface of the gate dielectric layer. The contact structure extends into the first source/drain structure. The top surface of the first fin structure is between a top surface and a bottom surface of the first source/drain structure.
    Type: Application
    Filed: August 13, 2018
    Publication date: March 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Kun-Mu LI, Wei-Yang LEE, Wen-Chu HSIAO
  • Publication number: 20190039957
    Abstract: A low-temperature co-fired microwave dielectric ceramic material includes: (a) 85 wt % to 99 wt % ceramic material comprising Mg2SiO4, Ca2SiO4, CaTiO3, and CaZrO3, wherein a weight ratio of Mg2SiO4 relative to Ca2SiO4 is of (1-x): x, a weight ratio of CaTiO3 relative to CaZrO3 is of y:z, and a weight ratio of entities of Mg2SiO4 and Ca2SiO4 relative to CaTiO3 is of (1-y-z):y, 0.2?x?0.7, 0.05?y?0.2, 0.05?z?0.4; and (b) 1 wt % to 15 wt % glass material composed of Li2O, BaO, SrO, CaO, B2O3, and SiO2.
    Type: Application
    Filed: October 11, 2018
    Publication date: February 7, 2019
    Inventors: Li-Wen Chu, Kuei-Chih Feng, Chih-Hao Liang
  • Patent number: D836771
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: December 25, 2018
    Assignee: AST PRODUCTS, INC.
    Inventors: Wen-Chu Tseng, Ming-Yen Shen, William Lee