Patents by Inventor Wen Fan

Wen Fan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • ORGANIC PACKAGING CARRIER
    Publication number: 20120241938
    Abstract: An organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and a sealing metal layer. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and includes at least a conductive layer and a sealing ring. The sealing ring is a closed ring. The sealing metal layer is located on the sealing ring, wherein a meterial of the sealing metal layer includes AgSn and is lead-free.
    Type: Application
    Filed: June 7, 2012
    Publication date: September 27, 2012
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Lung-Tai Chen, Tzong-Che Ho, Li-Chi Pan, Yu-Wen Fan
  • Metal gate transistor and resistor and method for fabricating the same
    Patent number: 8252657
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Grant
    Filed: March 27, 2011
    Date of Patent: August 28, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • METHOD FOR FABRICATING METAL GATE TRANSISTOR AND POLYSILICON RESISTOR
    Publication number: 20120214284
    Abstract: An integrated method includes fabricating a metal gate transistor and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a high resistance structure of the polysilicon resistor. When the dummy gate of the transistor is etched, the part of the high resistance structure is protected by the patterned photoresistor layer. The polysilicon resistor is formed simultaneously with the transistor. Furthermore, the polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Application
    Filed: May 2, 2012
    Publication date: August 23, 2012
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Method for fabricating metal gate and polysilicon resistor and related polysilicon resistor structure
    Patent number: 8193900
    Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Grant
    Filed: June 24, 2009
    Date of Patent: June 5, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • Method for reducing capacitance variation between capacitors
    Patent number: 8133792
    Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
    Type: Grant
    Filed: July 4, 2006
    Date of Patent: March 13, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Victor-Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
  • Structure of capacitor set
    Patent number: 8114752
    Abstract: A structure of a capacitor set is described, including at least two capacitors that are disposed at the same position on a substrate and include a first capacitor and a second capacitor. The first capacitor includes multiple first capacitor units electrically connected with each other in parallel. The second capacitor includes multiple second capacitor units electrically connected with each other in parallel. The first and the second capacitor units are arranged spatially intermixing with each other to form an array.
    Type: Grant
    Filed: February 6, 2010
    Date of Patent: February 14, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Victor Chiang Liang, Chien-Kuo Yang, Hua-Chou Tseng, Chun-Yao Ko, Cheng-Wen Fan, Yu-Ho Chiang, Chih-Yuh Tzeng
  • Semiconductor structure and method of forming the same
    Patent number: 8093118
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: January 10, 2012
    Assignee: United Microelectronics Corp.
    Inventors: Kun-Szu Tseng, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • VACUUM HERMETIC ORGANIC PACKAGING CARRIER
    Publication number: 20110297434
    Abstract: A vacuum hermetic organic packaging carrier is provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier.
    Type: Application
    Filed: May 20, 2011
    Publication date: December 8, 2011
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Lung-Tai Chen, Tzong-Che Ho, Li-Chi Pan, Yu-Wen Fan
  • Planet Wind Sail Mechanism
    Publication number: 20110209650
    Abstract: A planet wind sail mechanism includes a main axis, a first driving unit, and a wind sail body. The first driving further includes a rotation frame with a plurality of ribs, a transmission gear attached on the rib, a fixed gear which is disposed on the main axis and engaged with the transmission gear and a rotary gear is disposed on the edge of the rotation frame and engaged with the transmission gear. The wind sail body includes one rotation axis and the rotation axis is disposed on the edge of the rotation frame. When the wind sail body revolves along the main axis, both the rotary gear and the wind sail body also rotate itself. And the fixed gear rotates in an opposite direction with the rotary gear.
    Type: Application
    Filed: February 25, 2011
    Publication date: September 1, 2011
    Applicant: CHAMPION ENGINEERING TECHNOLOGY LTD
    Inventor: Nai-Wen Fan
  • Metal gate transistor and resistor and method for fabricating the same
    Patent number: 7994576
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Grant
    Filed: June 22, 2009
    Date of Patent: August 9, 2011
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20110171810
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Application
    Filed: March 27, 2011
    Publication date: July 14, 2011
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Vacuum hermetic organic packaging carrier and sensor device package
    Patent number: 7973454
    Abstract: A vacuum hermetic organic packaging carrier and a sensor device package are provided. The organic packaging carrier includes an organic substrate, a conductive circuit layer, and an inorganic hermetic insulation film. The organic substrate has a first surface. The conductive circuit layer is located on the first surface and exposes a portion of the first surface. The inorganic hermetic insulation film at least covers the exposed first surface to achieve an effect of completely hermetically sealing the organic packaging carrier.
    Type: Grant
    Filed: August 5, 2010
    Date of Patent: July 5, 2011
    Assignee: Industrial Technology Research Institute
    Inventors: Lung-Tai Chen, Tzong-Che Ho, Li-Chi Pan, Yu-Wen Fan
  • SEMICONDUCTOR DEVICE AND METHOD OF FORMING THE SAME
    Publication number: 20110156161
    Abstract: A semiconductor device including a substrate, a first device, a second device and an interlayer dielectric layer is provided. The substrate has a first area and a second area. The first device is disposed in the first area of the substrate and includes a first dielectric layer on the substrate and a metal gate on the first dielectric layer. The second device is in the second area of the substrate and includes a second dielectric layer on the substrate and, a polysilicon layer on the second dielectric layer. It is noted that the height of the polysilicon layer is less than that of the metal gate of the first device. The interlayer dielectric layer covers the second device.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kun-Szu Tseng, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • Biological Specimen Organizer
    Publication number: 20110132911
    Abstract: This invention relates to devices for storing reagents and biological specimens in fridge, freezers or liquid nitrogen. The device disclosed herein involves the use of coordinate style markings on the upper inner wall of the device that are not blocked once the spaces in the device are filled. The present device enables a user to easily fill spaces and retrieve specimens, and to coordinate with a laboratory information management system or other computer organizational system.
    Type: Application
    Filed: November 14, 2010
    Publication date: June 9, 2011
    Inventors: Jiandong Zhang, Ailin Guo, Wen Wang, Wen Fan
  • METAL GATE TRANSISTOR WITH RESISTOR
    Publication number: 20110073957
    Abstract: A resistor is disclosed. The resistor is disposed on a substrate, in which the resistor includes: a dielectric layer disposed on the substrate; a polysilicon structure disposed on the dielectric layer; two primary resistance structures disposed on the dielectric layer and at two ends of the polysilicon structure; and a plurality of secondary resistance structures disposed on the dielectric layer and interlaced with the polysilicon structures.
    Type: Application
    Filed: September 25, 2009
    Publication date: March 31, 2011
    Inventors: Kai-Ling Chiu, Victor-Chiang Liang, Chih-Yu Tseng, Kun-Szu Tseng, Cheng-Wen Fan, Hsin-Kai Chiang, Chih-Chen Hsueh
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
    Publication number: 20100327378
    Abstract: A semiconductor structure and a method of forming the same are provided. The semiconductor structure includes a substrate, a resistor and a metal gate structure. The substrate has a first area and a second area. The resistor is disposed in the first area, wherein the resistor does not include any metal layer. The metal gate structure is disposed in the second area.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Applicant: United Microelectronics Corp.
    Inventors: KUN-SZU TSENG, Che-Hua Hsu, Cheng-Wen Fan, Chih-Yu Tseng, Victor Chiang Liang
  • METHOD FOR FABRICATING METAL GATE AND POLYSILICON RESISTOR AND RELATED POLYSILICON RESISTOR STRUCTURE
    Publication number: 20100328022
    Abstract: An integrated method includes fabricating a metal gate and a polysilicon resistor structure. A photoresistor layer is defined by an SAB photo mask and covers a part of a polysilicon structure of the polysilicon resistor. When the gate conductor of a poly gate transistor is etched, the part of the polysilicon structure is protected by the patterned photoresistor layer. After the polysilicon resistor and the metal gate are formed. The polysilicon resistor still has sufficient resistance and includes two metal structures for electrical connection.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 30, 2010
    Inventors: Cheng-Wen Fan, Kun-Szu Tseng, Che-Hua Hsu, Chih-Yu Tseng, Victor-Chiang Liang
  • METAL GATE TRANSISTOR AND RESISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20100320544
    Abstract: A method for fabricating metal gate transistor and resistor is disclosed. The method includes the steps of: providing a substrate having a transistor region and a resistor region; forming a shallow trench isolation in the substrate of the resistor region; forming a tank in the shallow trench isolation of the resistor region; forming at least one gate in the transistor region and a resistor in the tank of the resistor region; and transforming the gate into a metal gate transistor.
    Type: Application
    Filed: June 22, 2009
    Publication date: December 23, 2010
    Inventors: Chih-Yu Tseng, Chien-Ting Lin, Kun-Szu Tseng, Cheng-Wen Fan, Victor-Chiang Liang
  • Method of producing UV-emitting magnesium pentaborate phosphors
    Patent number: 7846352
    Abstract: A method of producing a UV-emitting magnesium pentaborate phosphor is described. The method comprises combining a hydrated magnesium hexaborate with oxides of Y, Gd, Ce and Pr to form a mixture and firing the mixture in a slightly reducing atmosphere to form the phosphor. The hydrated magnesium hexaborate, which is preferably prepared as a precipitate, preferably has a formula MgB6O10.XH2O where X is from 4 to 6.
    Type: Grant
    Filed: February 13, 2008
    Date of Patent: December 7, 2010
    Assignee: OSRAM Sylvania Inc.
    Inventors: Gregory A. Marking, Chen-Wen Fan, Thomas M. Snyder
  • Moisture-resistant electroluminescent phosphor with high initial brightness and method of making
    Patent number: 7833437
    Abstract: The present invention is an electroluminescent phosphor wherein each individual phosphor particle is encapsulated in an inorganic coating applied by an atomic layer deposition (ALD) coating method. In a preferred embodiment, the coating is aluminum oxyhydroxide. The encapsulated phosphor shows an extreme insensitivity to atmospheric moisture and suffers only minor loss of initial brightness in lamps.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: November 16, 2010
    Assignee: Global Tungsten & Powders Corp.
    Inventors: Chen-Wen Fan, Tuan A. Dang, Joan M. Coveleskie, Frank A. Schwab, Dale E. Benjamin, David C. Sheppeck