Abstract: Provided are a reticle defect inspection method and system. The reticle defect inspection method includes: a reticle is provided; a reticle defect inspection system is provided, and when the reticle is placed on a station or leaves the station, defect inspection is continuously performed on the reticle to obtain defect information of each defect; a dynamic threshold of each defect is obtained from the defect information of each defect; and whether the dynamic threshold of each defect belongs to a threshold unacceptable by the inspection system is judged, and if so, warning processing is performed.

Abstract: A robot for transferring a wafer is disclosed. A blade of the robot includes a first sensor on an upper surface of the blade and the second sensor on a back surface of the blade. The first sensor is operable to align the blade with a wafer. The second sensor is operable to align the blade with a holder that holds the wafer.

Abstract: The present disclosure relates to a method for inhibiting a binding of a SARS-CoV-2 spike protein of a SARS-CoV-2 to an angiotensin-converting enzyme 2 including contacting the SARS-CoV-2 with a sufficient concentration of disulfiram, a method for inhibiting an activity of a main protease (Mpro) of SARS-CoV-2 including contacting a SARS-CoV-2 with a sufficient concentration of disulfiram, and a method for inhibiting an activity of a papain-like protease (PLpro) of SARS-CoV-2 including contacting a SARS-CoV-2 with a sufficient concentration of disulfiram. A method for inhibiting a replication or an infection of a SARS-CoV-2 in a cell includes contacting the cell with a sufficient concentration of disulfiram and a medical composition for use in a treatment of an infection of SARS-CoV-2 including a therapeutically effective amount of disulfiram are also provided.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: The disclosure provides a multi-voltage chip, including a regulator circuit, a high-voltage domain controller, a low-voltage domain controller, and a digital logic circuit. The regulator circuit receives and responds to a feedback signal, a regulating start signal, and a reference voltage to convert a system high voltage into a regulated voltage. The high-voltage domain controller receives a power signal and the system high voltage to provide the reference voltage and the regulating start signal. The low-voltage domain controller is coupled to the high-voltage domain controller and receives the regulated voltage to provide a system start signal in response to the regulating start signal. The digital logic circuit is coupled to the regulator circuit to receive the regulated voltage and provide the feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a plurality of gate structures arranged over a substrate and between adjacent ones of a plurality of source/drain regions within the substrate. A plurality of conductive contacts are electrically coupled to the plurality of source/drain regions. A first interconnect wire is arranged over the plurality of conductive contacts, and a second interconnect wire arranged over the first interconnect wire. A via rail contacts the first interconnect wire and the second interconnect wire. The via rail has an outer sidewall that faces an outermost edge of the plurality of source/drain regions and that is laterally separated from the outermost edge of the plurality of source/drain regions by a non-zero distance. The outer sidewall of the via rail continuously extends past two or more of the plurality of gate structures.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Abstract: A folding chair includes a left supporting frame member, a left leg, a left armrest, a left seat receiver, a left front support, a left rear support, a left front connecting member, a left rear connecting member, a left backrest support, a left front support pivot, a left rear support pivot, a left front pivot, a left rear pivot, a left backrest support pivot, a right supporting frame member, a right leg, a right armrest, a right seat receiver, a right front support, a right rear support, a right front connecting member, a right rear connecting member, a right backrest support, a right front support pivot, a right rear support pivot, a right front pivot, a right rear pivot, a right backrest support pivot, a front pivoting limiter, a rear pivoting limiter, a front pivotal connector, a rear pivotal connector, a seat and a backrest.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

Abstract: The present disclosure relates to a method for preventing or inhibiting a synthesis of viral RNA of SARS-CoV-2 in a cell including contacting the cell with a sufficient concentration of tafenoquine, boceprevir or narlaprevir and a method for inhibiting an activity of a main protease (Mpro) of SARS-CoV-2 including contacting a SARS-CoV-2 with a sufficient concentration of tafenoquine, boceprevir or narlaprevir. A medical composition for use in a treatment of an infection of SARS-CoV-2 including a therapeutically effective amount of tafenoquine, boceprevir or narlaprevir is also provided.

Abstract: The disclosure provides a multi-voltage chip, including a regulator circuit, a high-voltage domain controller, a low-voltage domain controller, and a digital logic circuit. The regulator circuit receives and responds to a feedback signal, a regulating start signal, and a reference voltage to convert a system high voltage into a regulated voltage. The high-voltage domain controller receives a power signal and the system high voltage to provide the reference voltage and the regulating start signal. The low-voltage domain controller is coupled to the high-voltage domain controller and receives the regulated voltage to provide a system start signal in response to the regulating start signal. The digital logic circuit is coupled to the regulator circuit to receive the regulated voltage and provide the feedback signal, and is coupled to the low-voltage domain controller to operate in response to the system start signal.

Abstract: The present invention relates to a jet structure of a fan rotor, which comprises a fan wheel and at least one connecting channel. The fan wheel has a hub and plural blades disposed on the circumferential side of the hub. The hub has a top portion and a sidewall. Each of the blades has an upper surface and a lower surface which form a high-pressure zone and a low-pressure zone, respectively. The connecting channel is provided with at least one first inlet disposed in the high-pressure zone and at least one first outlet disposed in the low-pressure zone. The first inlet and the first outlet are a first end and a second end of the connecting channel, respectively. By means of the design of the present invention, the effect of noise reduction can be achieved.

Abstract: A EUV lithography mask includes a substrate of a low thermal expansion material, a first reflective multilayer over the substrate, and a patterned reflective multilayer over the first reflective multilayer. The patterned reflective multilayer includes trenches through the patterned reflective multilayer. Each of the first reflective multilayer and the patterned reflective multilayer includes a stack of film pairs.

Abstract: Exfoliated nanoplatelets functionalized with a non-polar moiety, such as an ethylene or propylene derived polymer, are useful for forming composites, films, and polymer blends.

Abstract: In a medical image generation method, projection data of a scanned object is acquired during rotation of a radiographic source, and a scout image of the scanned object is generated in one scanning direction using corresponding projection data in two opposite scanning directions in the projection data. The scanning direction is used to represent a relative position relationship between the radiographic source and the scanned object. Using projection data in two opposite directions to generate a scout image in one direction during rotary scanning of a radiographic source can significantly shorten the generation time of the scout image.

Abstract: Embodiments of the present disclosure generally relate to methods for forming an organic light emitting diode (OLED) device. Forming the OLED device comprises depositing a first barrier layer on a substrate having an OLED structure disposed thereon. A first sublayer of a buffer layer is then deposited on the first barrier layer. The first sublayer of the buffer layer is cured with a mixed gas plasma. Curing the first sublayer comprises generating water from the mixed gas plasma in a process chamber in which the curing occurs. The deposition of the first sublayer and the curing of the first sublayer is repeated one or more times to form a completed buffer layer. A second barrier layer is then deposited on the completed buffer layer.

Abstract: A folding chair includes a left frame rod, right frame rod, front left leg rod, front right leg rod, left armrest rod, right armrest rod, left armrest supporting rod, right armrest supporting rod, left connecting rod, right connecting rod, left backrest rod, right backrest rod, first front supporting rod, second front supporting rod, first rear supporting rod, second rear supporting rod, left frame rotating component, right frame rotating component, left positioning slider, right positioning slider, left sliding component, right sliding component, left armrest fixing component, right armrest fixing component, left supporting rod sliding component, right supporting rod sliding component, leg shoes, backrest rod sliding components, front limiting components, seat portion and backrest portion.

Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.