Patents by Inventor Wen Hao

Wen Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for replacing a pattern in a layout
    Patent number: 8977991
    Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.
    Type: Grant
    Filed: October 31, 2013
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng
  • Adjustable viewing angle display device and method for driving the same
    Patent number: 8976098
    Abstract: Disclosed herein is an adjustable viewing angle display device. The display device includes a display panel composed of a first substrate, a second substrate, a display medium layer interposed therebetween, a first electrode, a second electrode and a third electrode. Pluralities of sub-pixels are defined in the display panel. The first and second electrodes are disposed on the first substrate in the sub-pixels. The first electrode is spaced apart from the second electrode. The third electrode is disposed on the second substrate. When the display device is operated in a narrow viewing angle mode, there exists a non-zero potential difference between the second electrode and the third electrode, and when the sub-pixel is at gray level of zero, the potential difference between the first electrode and the second electrode is not zero. A driving method for driving the display device is disclosed as well.
    Type: Grant
    Filed: July 18, 2013
    Date of Patent: March 10, 2015
    Assignee: AU Optronics Corporation
    Inventors: Chen-Feng Fan, Chao-Wei Yeh, Chih-Hsiang Yang, Chien-Huang Liao, Wen-Hao Hsu
  • Method for character correction
    Patent number: 8976118
    Abstract: A computer program product is provided and includes a non-transitory tangible storage medium readable by a processing circuit and on which instructions are stored for execution by the processing circuit for performing a method. The method includes enabling retrieval of a keyboard pressed sequence of characters of a first type, permitting a re-selection of characters of a second type, which are associated with the keyboard pressed sequence of the characters of the first type and permitting modification of the keyboard pressed sequence of the characters of the first type to initiate a search for and retrieval of characters of the second type.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Lei Chen, Jenny S. Li, Wen Hao Wang
  • CELL LAYOUT DESIGN AND METHOD
    Publication number: 20150067616
    Abstract: A method includes comparing one or more cells to a selection guideline and storing the cells that meet the selection guideline in a non-transient computer readable storage medium to create the cell library based on the comparing. The selection guideline identifies a suitable position of a boundary pin within a cell.
    Type: Application
    Filed: August 28, 2013
    Publication date: March 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Hsiung HSU, Yuan-Te HOU, Li-Chun TIEN, Hui-Zhong ZHUANG, Fang-Yu FAN, Wen-Hao CHEN, Ting Yu CHEN
  • Three-Dimensional Semiconductor Image Reconstruction Apparatus and Method
    Publication number: 20150060669
    Abstract: A system comprises an electron beam directed toward a three-dimensional object with one tilting angle and at least two azimuth angles, a detector configured to receive a plurality of scanning electron microscope (SEM) images from the three-dimensional object and a processor configured to calculate a height and a sidewall edge of the three-dimensional object.
    Type: Application
    Filed: November 7, 2014
    Publication date: March 5, 2015
    Inventors: Wen-Hao Cheng, Chih-Chiang Tu, Chung-Min Fu, Ajay Nandoriya
  • Static timing analysis method and system considering capacitive coupling and double patterning mask misalignment
    Patent number: 8972919
    Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hao Chen, Yi-Kan Cheng
  • Routing method
    Patent number: 8972910
    Abstract: A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.
    Type: Grant
    Filed: August 15, 2013
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yuan-Te Hou, Wen-Hao Chen, Chin-Hsiung Hsu, Meng-Kai Hsu
  • ROUTING METHOD
    Publication number: 20150052492
    Abstract: A method includes generating one or more routes usable for implementing a conductive path of an integrated circuit. A corresponding cost function value for the one or more routes is calculated according to a first cost function, including adjusting the corresponding cost function value based on whether the corresponding route is at least partially assigned to be formed in a conductive layer by a first patterning process or a second patterning process. The integrated circuit has electrical devices and the conductive layer, and the conductive layer has a first set of conductive lines formed by the first patterning process and a second set of conductive lines formed by the second patterning process. The first set of conductive lines has a unit resistance less than that of the second set of conductive lines. The conductive path electrically connects two of the electrical devices of the integrated circuit.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuan-Te HOU, Wen-Hao CHEN, Chin-Hsiung HSU, Meng-Kai HSU
  • PIXEL STRUCTURE
    Publication number: 20150049288
    Abstract: A pixel structure includes a patterned insulating layer and a patterned electrode layer. The patterned insulating layer includes a first area and a second area, and the patterned electrode layer includes a third layer and a fourth layer. The first area has a plurality of bar-shaped structures, the third area is a block electrode, and the fourth area is composed of a plurality of first bar-shaped electrodes. The third area is disposed opposite to the first area such that the third area is protruded according to the bar-shaped structures thereby forming a plurality of second bar-shaped electrodes. The fourth area is disposed opposite to the second area such that the first bar-shaped electrodes are formed on the second area.
    Type: Application
    Filed: May 27, 2014
    Publication date: February 19, 2015
    Applicant: AU Optronics Corporation
    Inventors: Chao-Wei YEH, Tien-Lun TING, Wen-Hao HSU
  • Logic-based multiple time programming memory cell compatible with generic CMOS processes
    Patent number: 8958245
    Abstract: The non-volatile memory cell includes a coupling device and a first select transistor. The coupling device is formed in a first conductivity region. The first select transistor is serially connected to a first floating gate transistor and a second select transistor, all formed in a second conductivity region. An electrode of the coupling device and a gate of the first floating gate transistor are a monolithically formed floating gate; wherein the first conductivity region and the second conductivity region are formed in a third conductivity region; wherein the first conductivity region, the second conductivity region, and the third conductivity region are wells.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Te-Hsun Hsu, Wei-Ren Chen, Wen-Hao Ching, Wen-Chuan Chang
  • Systems and methods for designing layouts for semiconductor device fabrication
    Patent number: 8959466
    Abstract: Systems and methods are provided for designing semiconductor device layouts. For example, an initial layout including multiple target features associated with semiconductor devices is received. One or more dummy features are determined to be inserted into the initial layout. The target features and the dummy features are assigned to multiple masks based at least in part on one or more mask-assignment rules. A final layout is generated for fabricating the semiconductor devices.
    Type: Grant
    Filed: November 14, 2013
    Date of Patent: February 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chin-Hsiung Hsu, Yuan-Te Hou, Wen-Hao Chen
  • HYBRID DESIGN RULE FOR DOUBLE PATTERNING
    Publication number: 20150040088
    Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.
    Type: Application
    Filed: October 25, 2013
    Publication date: February 5, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-I Huang, Wen-Hao Chen, Wen-Chun Huang
  • Pixel array
    Patent number: 8947472
    Abstract: A pixel array includes a first color pixel unit, a second color pixel unit and a third pixel unit, and the first, second and third pixel units respectively include a scan line, a data line, an active device electrically connected to the scan line and the data line and a first pixel electrode electrically connected to the active device. The first pixel electrode has at least one first slit, and a first acute angle is formed between an extending direction of the first slit and an extending direction of the scan line. Any two of the first acute angle of the first color pixel unit, the first acute angle of the second color pixel unit, and the first acute angle of the third color pixel unit are different.
    Type: Grant
    Filed: May 29, 2012
    Date of Patent: February 3, 2015
    Assignee: Au Optronics Corporation
    Inventors: Kun-Cheng Tien, Yu-Ching Wu, Ming-Huei Wu, Tien-Lun Ting, Chien-Huang Liao, Wen-Hao Hsu
  • Locating isolation points in an application under multi-tenant environment
    Patent number: 8949787
    Abstract: A computer implemented method for locating isolation points in an application under multi-tenant environment includes scanning, using a computer device an application by using scanning rules, to obtain potential isolation points and relationships between the potential isolation points; specifying at least one isolation point among the potential isolation points; and screening an isolation point from the potential isolation points by using relationships between the specified at least one isolation point and the remaining potential isolation points.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Wen Hao An, Hong Cai, Liya Fan, Bo Gao, Chang Jie Guo, Li Li Ma, Zhi Hu Wang, Min Jun Zhou
  • Hybrid design rule for double patterning
    Patent number: 8949758
    Abstract: Among other things, one or more systems and techniques for generating or implementing a hybrid design rule set are provide herein. A set of color design rules and a set of color agnostic design rules are generated and exposed for selective design rule assignment. In an embodiment, a first color design rule is assigned to a first polygon. In an embodiment, a first color agnostic design rule is assigned to a second polygon. In this way, color design rules and color agnostic design rules are selectively applied to polygons of a design layout. Color design rules are selected for space and design efficiency. Color agnostic rules are selected for conservative design layout for design ease. A design rule checking stage and a design rule fixing stage are performed such that the design layout is compliant after color decomposition without a second design rule fixing stage.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Cheng-I Huang, Wen-Hao Chen, Wen-Chun Huang
  • Method and Device for Loudness Level Determination
    Publication number: 20150031419
    Abstract: A method on a mobile device for providing an audio output to a user at a determined loudness level is described. A text input is received. A loudness level of an audio output, corresponding to the text input, is determined based on a volume setting of the mobile device and a non-linear adjustment of the volume setting. The audio output is provided to an audio output component at the determined loudness level.
    Type: Application
    Filed: December 27, 2013
    Publication date: January 29, 2015
    Applicant: Motorola Mobility LLC
    Inventors: Wen Hao Zhang, Prabhu Annabathula, Jonathan E. Eklund, Adrian M. Schuster, Andrew K. Wells
  • 3D DEVICE MODELING FOR FINFET DEVICES
    Publication number: 20150026657
    Abstract: Among other things, techniques and systems for 3D modeling of a FinFET device and for detecting a variation for a design layout based upon a 3D FinFET model are provided. For example, a fin height of a FinFET device is determined based upon imagery of the FinFET device. The fin height and a 2D FinFET model for the FinFET device are used to create a 3D FinFET model. The 3D FinFET model takes into account the fin height, which is evaluated to identify fin height variations amongst FinFET devices within the design layout. For example, a fin height variation is determined based upon a proximity pattern density, a fin pitch, a gate length, or other parameters/measurements. A voltage threshold variation is determined based upon the fin height variation. This allows the design layout to be modified to decrease the variation.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: Chung-min Fu, Meng-Fu You, Po-Hsiang Huang, Wen-Hao Cheng
  • Anti-relief fan frame body structure
    Patent number: 8936433
    Abstract: An anti-relief fan frame body structure includes a frame body and multiple anti-relief sections. The frame body has a receiving space and a shaft seat received in the receiving space. The frame body further has multiple flow guide members extending from a circumference of shaft seat to an inner circumference of the frame body to connect with the inner circumference of the frame body. The anti-relief sections are disposed on the inner circumference of the frame body between the flow guide members to increase the performance of the fan.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: January 20, 2015
    Assignee: Asia Vital Components Co., Ltd.
    Inventors: Wen-Hao Liu, Guan-Chen Yin
  • DOUBLE PATTERNING TECHNOLOGY (DPT) LAYOUT ROUTING
    Publication number: 20150012895
    Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Huang-Yu Chen, Fang-Yu Fan, Yuan-Te Hou, Wen-Hao Chen, Chung-Hsing Wang, Yi-Kan Cheng
  • Moving object detection method and image processing system for moving object detection
    Patent number: 8922651
    Abstract: A moving object detection method and an image processing system thereof are provided. First, a pixel-wise distance of a received image to a reference image is computed to obtain a distance map. A histogram analysis is performed on the distance map to obtain a distance distribution. An entropy value of the distance distribution is computed and a peak distance value which is with a maximum occurrence probability in the distance distribution is searched out. Then, by using a mapping rule, the entropy value and the peak distance value are transformed into a decision threshold value. The decision threshold value is applied in classifying the pixels of the distance map into a group of foreground attributes and a group of background attributes and thereby moving objects in the current image are obtained.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: December 30, 2014
    Assignee: Industrial Technology Research Institute
    Inventors: Tai-Hui Huang, Tsung-Chan Li, Wen-Hao Wang