Patents by Inventor Wen Hao
Wen Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9041540Abstract: The present invention provides a radio frequency identification tag gripper device, the technical scheme including: a first gripper portion; a second gripper portion, which generates a gripping force together with the first gripper portion; a radio frequency identification tag, a circuit portion of which is divided into at least a first section and a second section, an upper surface of the first section and a lower surface of the second section being coated with strong glue, wherein the upper surface of the first section is used to bond with a grip surface of the first gripper portion when gripped tightly, and the lower surface of the second section is used to produce a coupling force with a surface of the gripped object when gripped tightly. Utilizing the technical solution of the present invention, it is possible to further improve the security of monitoring of the radio frequency identification tag.Type: GrantFiled: February 27, 2013Date of Patent: May 26, 2015Assignee: International Business Machines CorporationInventors: Wen Hao An, Bo Gao, Peng Gao, Wei Sun, Xi Sun
-
Patent number: 9035361Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.Type: GrantFiled: April 26, 2013Date of Patent: May 19, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Lee-Chung Lu, Wen-Hao Chen, Yuan-Te Hou, Shen-Feng Chen, Meng-Fu You
-
Publication number: 20150125262Abstract: A series fan assembling structure includes a connection assembly, a first fan and a second fan. The connection assembly has a first connection member having a first end face and a second end face opposite to the first end face. A second connection member is disposed at an upper end of the first connection member to outward horizontally extend from the first end face. A third connection member is disposed at a lower end of the first connection member to outward horizontally extend from the second end face. A passage is formed at the centers of the first and second end faces. The first fan is mated with the first end face of the first connection member and horizontally connected with the second connection member. The second fan is mated with the second end face of the first connection member and horizontally connected with the third connection member.Type: ApplicationFiled: November 7, 2013Publication date: May 7, 2015Applicant: Asia Vital Components Co., Ltd.Inventor: Wen-Hao Liu
-
Patent number: 9026957Abstract: An embodiment of a feed-forward method of determining a photomask pattern is provided. The method includes providing design data associated with an integrated circuit device. A thickness of a coating layer to be used in fabricating the integrated circuit device is predicted based on the design data. This prediction is used to generate a gradating pattern. A photomask is formed having the gradating pattern.Type: GrantFiled: February 25, 2014Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Chu Liu, Kuei Shun Chen, Chih-Yang Yeh, Te-Chih Huang, Wen-Hao Liu, Ying-Chou Cheng, Boren Luo, Tsong-Hua Ou, Yu-Po Tang, Wen-Chun Huang, Ru-Gun Liu, Shu-Chen Lu, Yu Lun Liu, Yao-Ching Ku, Tsai-Sheng Gau
-
Patent number: 9022724Abstract: An anti-vibration serial fan structure includes a first frame having a first assembling side and a second frame having a second assembling for connecting to the first assembling side. The first assembling side is provided with at least one mounting post or mounting hole and at least one male or female connector. The second assembling side is correspondingly provided with at least one mounting hole or mounting post and at least one female or male connector. The male connector has a certain degree of elasticity, so that the engaged male and female connectors provide a vibration-absorbing effect to save additional cushioning elements, enabling the serial fan structure to have lowered assembling cost and minimized defects in assembling.Type: GrantFiled: February 1, 2012Date of Patent: May 5, 2015Assignee: Asia Vital Components Co., Ltd.Inventor: Wen-Hao Liu
-
Patent number: 9027028Abstract: A method and apparatus controls use of a computing resource by multiple tenants in DBaaS service. The method includes intercepting a task that is to access a computer resource, the task being an operating system process or thread; identifying a tenant that is in association with the task from the multiple tenants; determining other tasks of the tenant that access the computing resource; and controlling the use of the computing resource by the task, so that the total amount of usage of the computing resource by the task and the other tasks does not exceed the limit of usage of the computing resource for the tenant.Type: GrantFiled: November 26, 2012Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Wen Hao An, Li Ya Fan, Bo Gao, Chang Jie Guo, Berthold Reinwald, Wei Sun, Ning Wang, Zhi Hu Wang
-
Patent number: 9022722Abstract: A frame assembly of a ring-type fan with a pressure-releasing function includes a fan wheel, a pressuring-releasing portion, and a frame body. The fan wheel is received in an accommodating space of the frame body. The fan wheel has a hub and a plurality of blades. The pressure-releasing portion is formed on free ends of the blades and has a stopping wall and a flange extending from one end of the stopping wall. A pressure-releasing channel is formed between the stopping wall and an inner wall of the frame body. With the pressure-releasing portion being formed on the free ends of the blades, the present invention is capable of delaying the deceleration, improving the fan performance, and reducing its noise.Type: GrantFiled: November 15, 2011Date of Patent: May 5, 2015Assignee: Asia Vital Components Co., Ltd.Inventors: Wen-Hao Liu, Guan-Chen Yin
-
Patent number: 9026953Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.Type: GrantFiled: October 28, 2013Date of Patent: May 5, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Chin-Hsiung Hsu, Wen-Hao Chen, Chung-Hsing Wang
-
Patent number: 9019678Abstract: A protection component includes: a package substrate; a first fuse unit disposed in the package substrate, having a first fusing region; a second fuse unit disposed in the package substrate, having a second fusing region which is close to the first fusing region; and a first buried cave disposed in the package substrate corresponding to the first and second fusing regions. When one of the first and second fusing regions is blown out, the first buried cave assists energy of fuse melting to break the other of the first and second fusing regions.Type: GrantFiled: August 16, 2012Date of Patent: April 28, 2015Assignee: Industrial Technology Research InstituteInventors: Hsin-Hsien Yeh, Hong-Ching Lin, Tsung-Wen Chen, Wen-Hao Deng
-
Publication number: 20150107173Abstract: Disclosed are a metal curtain wall system of a monolayer structure and a construction method thereof. The metal curtain wall system comprises a plurality of composite material curtain wall units (1) that are produced in a numerical control manner and have complex models. The plurality of composite material curtain wall units (1) is spliced to form an inner-outer wall body model. Embedded members (2) are arranged in the composite material curtain wall units (1). Lead-out parts of the embedded members are oriented towards the inner and outer wall bodies and are fixed to inner and outer wall bodies. The composite material curtain wall units (1) in vertical adjacency are arrayed in a staggered manner. An elastic structural adhesive (3) is coated on surfaces of the composite material curtain wall units (1). Thin-type metal sheets (4) are covered on the elastic structural adhesive (3).Type: ApplicationFiled: May 18, 2012Publication date: April 23, 2015Applicant: Evergrow International Trading (Shanghai) Co.,Ltd.Inventors: Chuan Hul Ku, Wen Hao Ku
-
Publication number: 20150106779Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by forming an integrated chip (IC) design that is a graphical representation of an integrated chip. One or more low-pattern-density areas of the IC design are identified having a pattern density that results in a processing failure. The low-pattern-density areas are a subset of the IC design. The pattern density is adjusted within the low-pattern-density area by adding one or more dummy shapes within the low-pattern-density areas. A data preparation process is then performed on the IC design to modify shapes of the one or more dummy shapes within the low-pattern-density areas. By introducing dummy shapes into a local area, rather than into an entire integrated chip design, the demands of the subsequent data preparation process are reduced.Type: ApplicationFiled: October 11, 2013Publication date: April 16, 2015Inventors: Hung-Chun Wang, Ming-Hui Chih, Ping-Chieh Wu, Chun-Hung Wu, Wen-Hao Liu, Cheng-Hsuan Huang, Cheng-Kun Tsai, Wen-Chun Huang, Ru-Gun Liu
-
Publication number: 20150092498Abstract: A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.Type: ApplicationFiled: May 6, 2014Publication date: April 2, 2015Applicant: eMemory Technology Inc.Inventors: Wen-Hao Ching, Yen-Hsin Lai, Shih-Chen Wang
-
Publication number: 20150091955Abstract: A pixel array includes a first color pixel unit, a second color pixel unit and a third pixel unit, and the first, second and third pixel units respectively include a scan line, a data line, an active device electrically connected to the scan line and the data line and a first pixel electrode electrically connected to the active device. The first pixel electrode has at least one first slit, and a first acute angle is formed between an extending direction of the first slit and an extending direction of the scan line. Any two of the first acute angle of the first color pixel unit, the first acute angle of the second color pixel unit, and the first acute angle of the third color pixel unit are different.Type: ApplicationFiled: December 9, 2014Publication date: April 2, 2015Inventors: Kun-Cheng Tien, Yu-Ching Wu, Ming-Huei Wu, Tien-Lun Ting, Chien-Huang Liao, Wen-Hao Hsu
-
Publication number: 20150095857Abstract: A portion of a layout of a single layer of an integrated circuit is to be multi-patterned. A method for layout decomposition includes determining spacings between adjacent pairs of patterns, and generating a conflict graph having a plurality of sub-graphs, in which a respective vertex corresponds to each respective sub-graph. The patterns within each respective sub-graph are divided into at least a first group and a second group, each of which is assigned to be patterned on the single layer by a respectively different one of a first mask or a second mask. The method further include determining, in a processor, a count of color-rule violations in the plurality of patterns within each respective sub-graph based on a predetermined set of criteria; and within each sub-graph, assigning the first group of patterns in the sub-graph to the one of the first mask or the second mask which results in a smaller count of color-rule violations.Type: ApplicationFiled: October 2, 2013Publication date: April 2, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chin-Hsiung HSU, Chin-Chang HSU, Yuan-Te HOU, Godina HO, Wen-Hao CHEN, Wen-Ju YANG
-
Patent number: 8995060Abstract: A head-up display device includes an image module, a substrate, and an optical film. The image module has an emitting source, wherein the emitting source transmits at least one image. The substrate is disposed corresponding to the image module. The optical film is disposed on the substrate and includes at least one transmission layer, wherein each transmission layer has a plurality of transmitting column structures obliquely arranged side by side, and a longitudinal direction of the transmitting column structure has a tilt angle with respect to a normal of the substrate. The at least one image is transmitted to the optical film, and the obliquely disposed transmitting column structures cause the at least one image to scatter on the optical film.Type: GrantFiled: December 26, 2012Date of Patent: March 31, 2015Assignee: National Applied Research LaboratoriesInventors: Wen-Hao Cho, Bo-Huei Liao, Donyau Chiang, Cheng-Chung Lee
-
Patent number: 8989268Abstract: Method and apparatus for motion estimation for video processing. An embodiment of a method for motion estimation includes the following steps. In the course of motion estimation, integer motion estimation is performed with respect to a macroblock to generate a plurality of integer motion vectors. It is determined, according to a portion of the motion vectors, which correspond to a plurality of block modes, whether the integer motion vectors of each block mode are substantially equal to those of a corresponding upper-layer block mode of the block mode, so as to determine whether to perform or skip fractional motion estimation of the block mode, wherein each corresponding upper-layer block mode(s) of the block modes is greater than the block mode.Type: GrantFiled: November 29, 2010Date of Patent: March 24, 2015Assignee: Industrial Technology Research InstituteInventors: Yuan-Teng Chang, Wen-Hao Chung
-
Patent number: 8988643Abstract: A peep-proof display apparatus includes a plurality of sub-pixels disposed between a first substrate and a second substrate. Each sub-pixel includes a first conductive layer, a color filter layer, an isolation film, a light modulator layer, a second conductive layer, an insulation film and a third conductive layer. The color filter layer is disposed between the first conductive layer and the isolation film. The light modulator layer is disposed between the isolation film and the second conductive layer. The insulation film is disposed between the second and third conductive layers. In a first display mode, the light modulator layer is applied with an electric field parallel thereto. In a second display mode, the light modulator layer is applied with an electric field parallel thereto and an electric field perpendicular thereto.Type: GrantFiled: April 15, 2013Date of Patent: March 24, 2015Assignee: AU Optronics Corp.Inventors: Chih-Hsiang Yang, Chao-Wei Yeh, Chen-Feng Fan, Chien-Huang Liao, Wen-Hao Hsu
-
Publication number: 20150077444Abstract: A 2D/3D image displaying apparatus includes a sub-pixel, a first and second data lines and a gamma circuit. The sub-pixel includes a first portion and a second portion. The first and second data lines are coupled to the first and second portion of the sub-pixel, respectively. The gamma circuit transmits correlated gamma signals to a driving circuit for driving the first and second part of the sub-pixel via the first and second data lines when 2D image is to be displayed, and transmits a single gamma signal to the driving circuit for driving the first and second portion of the sub-pixel via the first and second data lines when 3D image is to be displayed.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventors: Chao-Yuan Chen, Wen-Hao Hsu, Ting-Jui Chang
-
Patent number: 8982026Abstract: A sub-pixel circuit, display panel and driving method of the display panel are provided. The display panel has a plurality of data lines, scan lines and sub-pixel circuits. At least one of the sub-pixel circuits is electrically coupled to one data line and three scan lines. The sub-pixel circuit determines whether to receive data from the coupled data line or not according to scan signals transmitted on the coupled three scan lines, and controls transmittance itself accordingly. Specifically, the scan signals transmitted on the coupled three scan lines are different from each other.Type: GrantFiled: June 21, 2012Date of Patent: March 17, 2015Assignee: AU Optronics Corp.Inventors: Yu-Ching Wu, Tien-Lun Ting, Kun-Cheng Tien, Chien-Huang Liao, Wen-Hao Hsu
-
Patent number: 8977991Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.Type: GrantFiled: October 31, 2013Date of Patent: March 10, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Huang-Yu Chen, Yuan-Te Hou, Chung-Min Fu, Chung-Hsing Wang, Wen-Hao Chen, Yi-Kan Cheng