Abstract: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.

Abstract: Among other things, one or more techniques and systems for layout re-decomposition of a new layout corresponding to a change order to an original layout associated with an integrated circuit are provided. The change order is applied to the original layout to create the new layout. The original layout comprises one or more original pattern portions assigned pattern colors that correspond to pattern masks. One or more new pattern portions within the new layout are assigned pattern colors such that the new layout has a relatively high color similarity with respect to the original layout. In this way, changes to the pattern masks are reduced, thus mitigating fabrication delay or costs that would otherwise result from significant changes to the pattern masks.

Abstract: A method comprises directing an electron beam toward a sidewall of a three-dimensional region of a semiconductor device with a tilting angle and a first azimuth angle, detecting a first projection distance of the sidewall through a detector placed over the semiconductor device, directing the electron beam toward the sidewall with the tilting angle and a second azimuth angle, detecting a second projection distance of the sidewall, calculating a height of the three-dimensional region using a first function, wherein the first function includes the first tilting angle, the first azimuth angle, the second azimuth angle and the projection distance of the sidewall and calculating a sidewall edge of the three-dimensional region using a second function, wherein the second function includes the first azimuth angle, the second azimuth angle and the projection distance of the sidewall.

Abstract: A pixel structure of a display panel includes a gate line, a first data line, a second data line, a first active switching device, a second active switching device, a first pixel electrode and a second pixel electrode. The first pixel electrode is electrically connected to the first active switching device. The first pixel electrode includes a first main electrode disposed adjacent to one side of the first data line, and a second main electrode disposed adjacent to one side of the second data line. The second pixel electrode is electrically connected to the second active switching device. The second pixel electrode is disposed between the first main electrode and the second main electrode of the first pixel electrode.

Abstract: A liquid crystal display (LCD) panel divided into a first area and a second area is provided. The first and second areas both include first sub-pixels and second sub-pixels. Each first sub-pixel provides a first main alignment vector; each second sub-pixel provides a second main alignment vector having a direction opposite to that of the first main alignment vector. The LCD panel has first sub-pixel units and second sub-pixel units arranged in arrays. Each first sub-pixel unit includes one first sub-pixel and one second sub-pixel sequentially arranged from top to bottom in a column direction. Each second sub-pixel unit includes one first sub-pixel and one second sub-pixel sequentially arranged from bottom to top in the column direction. In any one of the first area and the second area, multiple first sub-pixel units and multiple second sub-pixel units are arranged together in a same row.

Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.

Abstract: A pixel structure including a first active device, a second active device, a first pixel electrode, a second pixel electrode, a third pixel electrode, a coupling electrode, and a capacitance electrode is provided. The first pixel electrode connected to the first active device and defines a first to a fourth liquid crystal alignment domain having different alignment directions. The second pixel electrode is connected to the coupling electrode and defines a fifth to an eighth liquid crystal alignment domain having different alignment directions. The third pixel electrode is connected to the second active device and defines a ninth and a tenth liquid crystal alignment domain. The coupling electrode is connected between the first active device and the second active device and extended to pass through the first, the second, and the third pixel electrodes. The capacitance electrode respectively overlaps parts of the first, the second, and the third pixel electrodes.

Abstract: A pixel structure includes a first conductive layer, a stacked layer, and a third conductive layer. The first conductive layer includes a first gate, a first scan line connected to the first gate, and a capacitor electrode separated from the first scan line. The stacked layer includes a semiconductor layer and a second conductive layer. The second conductive layer includes a data line, a first source connected to the data line, a second source, a first drain, a second drain, a connecting electrode connected to the second source and electrically connected to the first drain, and a coupling electrode connected to the second drain. The third conductive layer includes a first pixel electrode connected to the first drain, a second pixel electrode electrically connected to the connecting electrode, a first extending portion, and a second extending portion.

Abstract: High performance clock distributions and similar wiring networks require improvements in reliability and performance. This is especially true when hierarchical wiring with different metal thicknesses is employed and when a smaller number of large, higher-power buffers are used to reduce timing variability. Routing of critical nets improves robustness, reliability, and resistance while minimizing track and power usage. The method further optimizes the use of multiple physical pins on buffers to achieve desired electrical criteria. This involves optimal selection of additional routing beyond what is needed to satisfy simple connectivity. The routing involves an iterative process to select and evaluate additional possible routes on multiple layers. Each iteration involves extraction and simulation or estimation, and additional routes are added until the desired electrical criteria are met.

Abstract: A LCD panel in which a pixel has a first sub-pixel area and a second sub-pixel area, each area having a storage capacitor. Each pixel has a first gate line for providing a first gate-line signal for charging the first and second storage capacitors, and a second gate line for providing a second gate-line signal for removing part of the charges in the second storage capacitor to a third capacitor after the first gate-line signal has passed. The width of the first and second gate-line signals and their timing can be varied so that the first gate-line signal provided to a row can be used as the second gate-line signal to one of the preceding rows. In some embodiments, a pixel in each row has a duplicate pixel arranged to similarly receive the first and second gate-line signals, but data signals are received from different data lines.

Abstract: Methods are disclosed of modifying an integrated circuit (IC) design that utilizes multiple patterning technology (MPT). The methods include configuring a first layout of an integrated circuit, having at least one layer with features to be formed utilizing fabrication by at least two masks. The at least one layer includes a plurality of active cells and a plurality of spare cells. A second layout is configured to re-route the spare cells and active cells, wherein the re-routing utilizes at least a portion of the plurality of spare cells. Fewer than all of the at least two masks are replaced to configure the second layout.

Abstract: A tri-state liquid crystal display panel includes a first substrate, a second substrate, a liquid crystal layer, a first electrode, a second electrode, a third electrode and a fourth electrode. The first substrate and the second substrate are disposed oppositely. The liquid crystal layer disposed between the first substrate and the second substrate includes a plurality of polymer network liquid crystals. The first electrode is disposed between the first substrate and the liquid crystal layer, the second electrode is disposed between the second substrate and the liquid crystal layer, and the first and second electrodes include planar electrodes. The third and fourth electrodes are disposed between the first substrate and the liquid crystal layer, and the third and fourth electrodes include patterned electrodes. The tri-state liquid crystal display panel has a transmission state display mode, a dark state display mode and a haze state display mode.

Abstract: A mercaptoalkylsilatrane derivative having protecting group and a method of manufacturing the same. The mercaptoalkylsilatrane derivative includes: mercaptoalkylsilatrane compound having a mercapto group; a protecting group bonding to sulfur of the mercapto group, wherein the protecting group is used to avoid the chemical reaction of the mercapto group with reactive chemical species, e.g., oxygen, ketone, and aldehyde, etc. Besides, the manufacturing method thereof includes the steps of: providing silane compound having the mercapto group; bonding the protecting group to the mercapto group of the silane compound; performing the chemical reaction of triethanolamine with the silane compound having the protecting group for manufacturing the mercaptoalkylsilatrane derivative having the protecting group.

Abstract: A method for fixing metal onto a surface of the substrate. The present method includes steps of: providing a substrate and a mercaptoalkylsilatrane compound; dissolving the mercaptoalkylsilatrane compound in a solvent; performing a condensation reaction of the substrate with and the dissolved mercaptoalkylsilatrane compound to complete the surface modification of the substrate; and performing a covalent bonding process to metal with the mercaptoalkylsilatrane compound already modified onto the surface of the substrate to fix the metal onto the surface of the substrate.

Abstract: One or more techniques or systems for determining double patterning technology (DPT) layout routing compliance are provided herein. For example, a layout routing component of a system is configured to assign a pin loop value to a pin loop. In some embodiments, the pin loop value is assigned based on a mask assignment of a pin of the pin loop. In some embodiments, the pin loop value is assigned based on a number of nodes associated with the pin loop. DPT compliance or a DPT violation is determined for the pin loop based on the pin loop value. In this manner, odd loop detection associated with DPT layout routing is provided because a DPT violation results in generation of an additional instance of a net, for example. Detecting an odd loop allows a design to be redesigned before fabrication, where the odd loop would present undesired issues.

Abstract: A method includes patterning a layer over a substrate with a first metal pattern; using a cut mask in a first position relative to the substrate to perform a first cut patterning for removing material from a first region within the first pattern; and using the same cut mask to perform a second cut patterning while in a second position relative to the same layer over the substrate, for removing material from a second region in a second metal pattern of the same layer over the substrate.

Abstract: The present disclosure relates to a method of forming a reusable cut mask or trim mask that can be used for multiple design levels, and an associated apparatus. In some embodiments, the method is performed by determining positions of a plurality of mask cuts for a reusable cut mask or a reusable trim mask. Shapes are then routed along a routing path having a plurality of design levels. The routing path intersects one or more of the plurality of mask cuts at positions that form distinct shapes that connect nodes of an integrated chip sharing a same electric network. By routing shapes on a plurality of design levels to intersect one or more of the plurality of mask cuts, the cut masks can be reused between the plurality of levels, therefore decreasing mask costs during fabrication.

Abstract: An integrated circuit structure includes a plurality of power or ground rails for an integrated circuit, the plurality of power or ground rails vertically separated on a plane, a plurality of functional cells between the plurality of power rails or between the plurality of ground rails or both, and a jumper connection between the vertically separated power rails or ground rails, the jumper connection within a vertically aligned gap among the plurality of functional cells. A method of mitigating IR drop and electromigration affects in an integrated circuit includes forming a plurality of power rails or ground rails, each of the power rails or ground rails on separate vertical levels of a plane of an integrated circuit layout and connecting with a jumper connection at least two power rails or two ground rails, the jumper connection within a vertically aligned gap among cells of the integrated circuit.

Abstract: Some embodiments of the present disclosure relates to a method and apparatus to achieve a layout that is compatible with a multiple-patterning process. Two or more unit cells are constructed with layouts which satisfy the properties of the multiple-patterning process, and are each decomposed into two or more colors to support the multiple-patterning process. An active layout feature is merged with a dummy wire at a shared boundary between two unit cells. In the event of a short between two active layout features at the shared boundary, an automatic post-layout method can rearrange the layout features in a vicinity of the shared boundary to separate the active layout features to achieve cell functionality while satisfying the multiple-patterning properties.