Abstract: The present invention provides a method of fabricating an erasable programmable single-poly nonvolatile memory, comprising the steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covering a surface of the first area, wherein the second gate oxide layer extends to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covering the first and the second gate oxide layers; and defining a second type doped region in the DDD region and defining first type doped regions in the second type well region.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: An electronic device including a NAND flash memory, an auxiliary memory, and a controller is provided. A code for detecting a read command sequence of the NAND flash memory is stored in the auxiliary memory. During a boot procedure of the electronic device, the controller reads the code from the auxiliary memory and executes the code to obtain the read command sequence of the NAND flash memory, so as to access content stored in the NAND flash memory according to the read command sequence.

Abstract: A display apparatus includes a display panel disposed between a first polarizer and a second polarizer and having at least one first area and at least one second area. A first light-transmission axis direction of the first polarizer is substantially perpendicular to a second light-transmission axis direction of the second polarizer. The first light-transmission axis direction intersects a horizontal axis direction by about 45 degrees. When the display panel is in a narrow viewing angle display mode, the first and second areas have different brightness in a side viewing angle direction but have the same brightness in and around a normal viewing angle direction. When the display panel is in a wide viewing angle display mode, the first and second areas have substantially the same brightness in various viewing angle directions.

Abstract: A solar panel has a plurality of heat collecting manifold, a water inlet tube and a water outlet tube that are formed as one body by plastic molding, so that the heat collecting manifold can be vertically arranged between the water inlet tube and water outlet tube, and connected therewith. The solar panel is also formed as one body by plastic molding, so a rib piece can be used to connect between the collecting manifold. In one embodiment, when the collecting manifold of the solar panel is formed, every sectional surface of the collecting manifold can be formed as hexagonal or octagonal, so every sectional surface thereof can be used as a force-receiving portion. Also, one side of the rib piece has a recessed portion to enable the other side thereof to relatively protrude to form a resilient portion, and the recessed portion and resilient portion are all V-shaped.

Abstract: Embodiments relate to manipulating a multi-tenant database, wherein the multi-tenant database comprises one or more source databases for storing tenant data. An aspect includes receiving a database operation request for one or more tenant-specific logic views, wherein the tenant-specific logic views are created for respective tenants based on mapping information pointing to the one or more source databases included in the multi-tenant database and multi-tenant metadata. Another aspect includes acquiring the mapping information related to the database operation request and pointing to the one or more source databases included in the multi-tenant database. Yet another aspect includes performing a database operation corresponding to the database operation requested for the one or more source databases based on the acquired mapping information.

Abstract: A pixel array including a plurality of scan lines, data lines, and sub-pixels is provided. Each of the sub-pixels arranged in the nth row includes a first switch, a first pixel electrode, a second switch, a third switch, and a second pixel electrode. The first switch and the second switch are electrically connected to the nth scan line and the mth data line. The first switch and the first pixel electrode are electrically connected. The second switch has a first signal output terminal. The third switch is electrically connected to the (n+i)th scan line. The third switch has a signal input terminal electrically connected to the first signal output terminal and a second signal output terminal. The first signal output terminal is electrically insulated from the first pixel electrode and the second pixel electrode. The first signal output terminal extends to the underneath of the second pixel electrode.

Abstract: A hub device includes a first chip, a second chip and an external memory device. The first chip includes at least a first upstream port and multiple first downstream ports. The second chip includes at least a second upstream port and multiple second downstream ports. The external memory device stores firmware data corresponding to the first chip and the second chip. One of the first downstream ports of the first chip is coupled to the second upstream port of the second chip to form a tiered hub. The first chip and the second chip are sequentially enabled and the first chip and the second chip sequentially load the corresponding firmware data.

Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analyses is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

Abstract: A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell provides a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further provides two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

Abstract: Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a semiconductor device includes a workpiece and a plurality of first conductive lines disposed over the workpiece in a metallization layer. A plurality of second conductive lines is disposed over the workpiece in the metallization layer. The plurality of second conductive lines comprises a greater vertical height in a cross-sectional view of the workpiece than a vertical height of the plurality of first conductive lines.

Abstract: The present invention provides a rotor balance device and a method thereof. The device includes a balance measurement unit and at least one laser unit. The balance measurement unit has a correcting platen for supporting the rotor and at least one sensor. The laser unit receives a sensing signal outputted by the sensor to identify at least one position to be removed on the rotor and controls a laser beam to illuminate the position to be removed. By the inventive device and method, an improved degree of balance and reduced working hours can be obtained.

Abstract: A method for analyzing an IC design, comprises: using a computer implemented electronic design automation tool to perform a parasitic RC extraction for a layout of the IC design, the parasitic RC extraction outputting for each of a plurality of routing paths, a nominal capacitive coupling, a minimum capacitive coupling and a maximum capacitive coupling, where the minimum and maximum capacitive couplings correspond to circuit patterning in the presence of double patterning mask misalignments; and performing one of a setup time analysis or a hold time analysis of the IC design using a computer implemented static timing analysis tool. For a given flip-flop having a launch path and a capture path, the setup or hold time analysis is performed using the minimum capacitive coupling for one of the launch and capture paths and the maximum capacitive coupling for the other of the launch and capture paths.

Abstract: A method comprises (a) providing an integrated circuit (IC) layout comprising data representing a plurality of circuit patterns to be formed on or in a single layer of an IC by multi-patterning; (b) dividing the plurality of circuit patterns into two or more groups; (c) assigning the circuit patterns within each group to a respective mask to provide mask assignment data, for forming each group of circuit patterns on or in the single layer of the IC; (d) compressing the mask assignment data; and (e) storing the compressed mask assignment data to a non-transitory machine readable storage medium for use by an electronic design automation tool configured for reconstructing the mask assignment data from the compressed data.

Abstract: A received layout identifies a plurality of circuit components to be included in an integrated circuit (IC) layer for double patterning the layer using two photomasks, the layout including a plurality of first patterns to be included in the first photomask and at least one second pattern to be included in the second photomask. A selected one of the first patterns has first and second endpoints, to be replaced by a replacement pattern connecting the first endpoint to a third endpoint. At least one respective keep-out region is provided adjacent to each respective remaining first pattern except for the selected first pattern. Data are generated representing the replacement pattern, such that no part of the replacement pattern is formed in any of the keep-out regions. Data representing the remaining first patterns and the replacement pattern are output.

Abstract: A display apparatus includes a display panel disposed between a first polarizer and a second polarizer and having at least one first area and at least one second area. A first light-transmission axis direction of the first polarizer is substantially perpendicular to a second light-transmission axis direction of the second polarizer. The first light-transmission axis direction intersects a horizontal axis direction by about 45 degrees. When the display panel is in a narrow viewing angle display mode, the first and second areas have different brightness in a side viewing angle direction but have the same brightness in and around a normal viewing angle direction. When the display panel is in a wide viewing angle display mode, the first and second areas have substantially the same brightness in various viewing angle directions.

Abstract: A ring-type fan includes a frame having a receiving space defined between an air inlet and an air outlet thereof and being provided along an inner side of the air outlet with an inward projected wall portion; an impeller assembly rotatably mounted in the receiving space and including spaced impellers outward extended from a hub, and a ring member connected to radially outer ends of the impellers and externally provided with a circle of stop section, which and the projected wall portion together define an air passage between them; and at least one pressure relief section defining an airflow guide on the frame to communicate with the receiving space and the air passage. Any backflow can be guided out of the frame via the air passage and the pressure relief section without interfering with the inflow of air, allowing the ring-type fan to have upgraded heat dissipation performance.

Abstract: An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: A fan with integrated vibration absorbing structure includes a fan frame, a hub-blade assembly, and at least one vibration absorber. The fan frame includes a base and at least one side wall formed around the base, and the hub-blade assembly is arranged in the fan frame. The at least one vibration absorber is provided on the at least one side wall to project therefrom for absorbing vibration produced by the fan during the operation thereof. Therefore, with the vibration absorbers integrated into the fan frame, it is no longer necessary to provide any additional vibration-absorbing member while upgraded vibration-absorbing effect can be achieved. Meanwhile, the fan can be more conveniently mounted at reduced mounting cost.

Abstract: A method, an apparatus, and a system for locating sensor data. The method includes the steps of: obtaining an index table; intercepting a query for sensor data in runtime; extracting a characteristic parameter from a query condition; locating a block identifier of matching sensor data storage blocks in the index table by using the characteristic parameter; and loading the storage blocks into a memory space of a working processor; where the index table contains mapping relationships between block identifiers of sensor data storage blocks and characteristic attributes of sensor data.