Abstract: A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

Abstract: A method for making a chalcopyrite-type compound includes reacting a reaction mixture in a solvent under a reaction temperature and a reaction pressure to form the chalcopyrite-type compound. The reaction mixture includes at least one first compound and at least one second compound. The first compound contains M1 and A. The reaction temperature ranges from 130-280° C. and the reaction pressure is greater than 3 Kg/cm2. The second compound contains M2 and A. M1 is selected from Cu, Au, Ag, Na, Li and K, M2 is selected from In, Ga, Al, Ti, Zn, Cd, Sn, Mg, and combinations thereof, and A is selected from S, Se, Te, and combinations thereof.

Abstract: The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.

Abstract: A display panel includes a pair of substrates, a pixel structure, and a display medium layer disposed between the pair of substrates. The pixel structure is disposed on one of the substrates, and includes first and second sub-pixels. The first sub-pixel includes a first pixel electrode, wherein the first pixel electrode has a first spacing in a first main region and has a second spacing in a first minor region, wherein the second spacing is smaller than the first spacing. The second sub-pixel includes a second pixel electrode, wherein the second pixel electrode has a third spacing in a second main region and has a fourth spacing in a second minor region, wherein the fourth spacing is larger than or equal to the third spacing, and wherein the first spacing is larger than the third spacing.

Abstract: A stereo display including a display panel and a light shieldable element is provided. The display panel has at least two sub-pixel regions. Each sub-pixel region is configured with at least a first pixel electrode to define a first sub-region. The light shieldable element is disposed in front of the sub-pixel regions. Each first pixel electrode has a first shieldable region shielded by the light shieldable element and a first non-shielding region exposed by the light shieldable element. The first shieldable region is closer to the scan line than the first non-shielding region. A horizontal direction is defined as a connection line of two eyes of a user watching the stereo display. A total length A of each sub-pixel region and a length B of the first shieldable region in a predetermined direction intersected to the horizontal direction comply with a relationship that (B/A)×100% is substantially from 1.61% to 47.9%.

Abstract: Embodiments of the present disclosure provide methods and apparatuses for integrated circuits. An exemplary integrated circuit (IC) method includes providing an IC design layout that includes a design feature; determining a dimensional difference between the design feature and a corresponding developed photoresist feature of a photoresist layer; modifying the CD of the design feature to compensate for the difference, thereby generating a modified IC design layout; and making a mask using the modified IC design layout.

Abstract: The present invention relates to multi-user analytical system and corresponding device and method. The device includes an interception module configured to intercept a user's request for a first core object, wherein the first core object belongs to core object; a transformation module configured to create, in response to the request being a creation request, the first core object specific to the user; a mapping module configured to interpret, in response to the request being a non-creation request, the request as a request for the first core object specific to the user. The present invention also includes an isolation method for the multi-user analytical system. The technical solutions provided in the present invention can effectively enable multiple users to share physical resources in the analytical system, and the users are isolated from each other in a substantially transparent way.

Abstract: The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

Abstract: An interconnect structure including a bottom layer over a substrate, where the bottom layer includes at least one bottom layer line and at least one bottom layer via. The interconnect structure further includes a transition layer over the bottom layer, where the transition layer includes at least one transition layer line and at least one transition layer via. The interconnect structure further includes a top layer over the transition layer, where the top layer includes at least one top layer line and at least one top layer via. The at least one transition layer via has a cross sectional area at least 30% less than a cross sectional area of the at least one top layer via.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a first PMOS transistor comprising a select gate, a first source/drain region, and a second source/drain region, wherein the select gate is connected to a select gate voltage, and the first source/drain region is connected to a source line voltage; a second PMOS transistor comprising the second source/drain region, a third source/drain region, and a floating gate, wherein the third source/drain region is connected to a bit line voltage and the first, second and third source/drain regions are constructed in a N-well region; and an erase gate region adjacent to the floating gate, wherein the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region; wherein the N-well region and the P-well region are formed in the substrate structure.

Abstract: An erasable programmable single-poly nonvolatile memory includes a substrate structure; a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region, wherein the channel region is formed in a N-well region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region and the erase gate region comprises a n-type source/drain region connected to an erase line voltage and a P-well region. The N-well and P-well region are formed in the substrate structure. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: An display device package including a first substrate, an display device, a second substrate, a welding glue, and a first adhesive layer is provided. The display device is disposed on the first substrate. The second substrate is disposed above the first substrate and the display device. The welding glue is welded with the first substrate and the second substrate and surrounds the display device, wherein the welding glue has a continuous pattern. The first adhesive layer is adhered to the first substrate and the second substrate, wherein the first adhesive layer is disposed between the display device and the welding glue and surrounds the display device, and the material of the first adhesive layer and the material of the welding glue are different.

Abstract: A standard cell semiconductor integrated circuit device design provides a standard cell semiconductor device that includes first standard cells and user-defined target standard cells which consume more power or include other operational characteristics that differ from the operational characteristics of the first standard cells. The standard cells are routed to ground and power wires using one power rail and the target cells are routed to the ground and power lines using the first power rail and a second power rail to alleviate electromigration in either of the power rails. The two power rails include an upper power rail and a lower power rail. An intermediate conductive layer may be disposed between the upper and lower power rails to provide for signal routing by lateral interconnection between cells.

Abstract: In embodiments of content control based on data link context, a portable electronic device (102) detects when communicatively linked to a media rendering device (114) via a data link (122). The portable electronic device (102) can then determine whether the data link (122) was previously utilized to communicatively link the portable electronic device (102) to the media rendering device (114). The portable electronic device (102) can then initiate a media control selection menu (128) for display on the portable electronic device (102) if the data link (122) was not previously utilized. Alternatively, the portable electronic device (102) can initiate a media control interface (126) for display on the portable electronic device (102) if the data link (122) was previously utilized, where the media control interface (126) is implemented for user-selection to control media content (106) that is rendered by the media rendering device (114).

Abstract: An erasable programmable single-poly nonvolatile memory includes a floating gate transistor having a floating gate, a gate oxide layer under the floating gate, and a channel region; and an erase gate region, wherein the floating gate is extended to and is adjacent to the erase gate region. The gate oxide layer comprises a first portion above the channel region of the floating gate transistor and a second portion above the erase gate region, and a thickness of the first portion of the gate oxide layer is different from a thickness of the second portion of the gate oxide layer.

Abstract: The present invention provides method of fabricating an erasable programmable single-poly nonvolatile memory, comprising steps of: defining a first area and a second area in a first type substrate; forming a second type well region in the first area; forming a first gate oxide layer and a second gate oxide layer covered on a surface of the first area, wherein the second gate oxide layer is extended to and is adjacent to the second area; forming a DDD region in the second area; etching a portion of the second gate oxide layer above the second area; forming two polysilicon gates covered on the first and the second gate oxide layers; and defining a second type doped region in the DDD region and a first type doped regions in the second type well region.

Abstract: A method, system and computer program for processing materialized tables in a multi-tenant application system, wherein in the multi-tenant application system, a plurality of tenants share one or more basic-tables. According to the data access history information of the plurality of tenants, an update pattern analyzer analyzes the similarity of the update patterns for one or more basic-tables by the plurality of tenants. Furthermore, according to the similarity analyzed by the update pattern analyzer, a tenant grouping means groups the plurality of tenants into a plurality of tenant groups. Additionally, according to the tenant groups grouped by the tenant grouping means, a materialized table constructor constructs the tenant group materialized tables from the one or more basic-tables.

Abstract: The present disclosure provides integrated circuit methods for target-based dummy insertion. A method includes providing an integrated circuit (IC) design layout, and providing a thermal model for simulating thermal effect on the IC design layout, the thermal model including optical simulation and silicon calibration. The method further includes providing a convolution of the thermal model and the IC design layout to generate a thermal image profile of the IC design layout, defining a thermal target for optimizing thermal uniformity across the thermal image profile, comparing the thermal target and the thermal image profile to determine a difference data, and performing thermal dummy insertion to the IC design layout based on the difference data to provide a target-based IC design layout.

Abstract: A method comprises: accessing a persistent, machine readable storage medium containing data representing an integrated circuit (IC) design to be fabricated using multi-patterning; identifying at least one network of conductive patterns configured to transmit signals that substantially impact timing of at least one circuit in the IC; pre-grouping the at least one network of conductive patterns in a first group; and electronically providing data to an electronic design automation (EDA) tool to cause inclusion in a first single photomask of all portions of the patterns within the first group that are to be formed in a single layer of the IC, wherein the single layer is to be multi-patterned using at least two photomasks.

Abstract: An anti-vibration serial fan structure includes a first frame having a first assembling side and a second frame having a second assembling for connecting to the first assembling side. The first assembling side is provided with at least one mounting post or mounting hole and at least one male or female connector. The second assembling side is correspondingly provided with at least one mounting hole or mounting post and at least one female or male connector. The male connector has a certain degree of elasticity, so that the engaged male and female connectors provide a vibration-absorbing effect to save additional cushioning elements, enabling the serial fan structure to have lowered assembling cost and minimized defects in assembling.