Abstract: A method includes: providing a first layout of a first layer over a substrate, the first layer having at least one metal pattern, and generating a second layout by placing a cut mask at a first position relative to the substrate to remove material from a first region of the at least one metal pattern to provide a first metal pattern and placing the cut mask at a second position relative to the first layer over the substrate to remove material from a second region of the at least one metal pattern to provide a second metal pattern.

Abstract: A method of forming an integrated circuit includes placing a first and a second standard cell layout design of the integrated circuit on a layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height. Placing the first standard cell layout design includes placing a first set of pin layout patterns on a first layout level over a first set of gridlines, extending in a first direction, and having a first width in a second direction. Placing the second standard cell layout design includes placing a second set of pin layout patterns on the first layout level over a second set of gridlines, extending in the first direction, and having a second width in the second direction.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Abstract: A probe card for high-frequency testing is provided. The probe card includes a substrate, a flexible substrate, a probe, and at least one movable conductive pillar. The substrate has a first surface, a second surface, and at least one first through hole. The flexible substrate is disposed on the second surface of the substrate and has at least one second through hole. The second through hole and the first through hole correspond to each other. The probe is disposed on the second surface of the substrate, and is electrically connected to the flexible substrate. The movable conductive pillar movably passes through the first through hole and the second through hole.

Abstract: Provided are a reticle defect inspection method and system. The reticle defect inspection method includes: a reticle is provided; a reticle defect inspection system is provided, and when the reticle is placed on a station or leaves the station, defect inspection is continuously performed on the reticle to obtain defect information of each defect; a dynamic threshold of each defect is obtained from the defect information of each defect; and whether the dynamic threshold of each defect belongs to a threshold unacceptable by the inspection system is judged, and if so, warning processing is performed.

Abstract: A charging circuitry includes a power electronic converter, a current sensor, a voltage boost/buck controller and a charging mode controller. The power electronic converter is configured to charge or discharge a supercapacitor according to a control command. The current sensor is coupled to the supercapacitor for detecting a first sensed voltage and a second sensed voltage. The voltage boost/buck controller is configured to generate the control command and a current command according to the first and second sensed voltages and an overall feedback. The charging mode controller is configured to generate a current feedback and a voltage feedback to the voltage boost/buck controller according to a driving voltage, the current command and a third sensed voltage of the supercapacitor. The third sensed voltage, the current feedback and the voltage feedback are superposed as the overall feedback and then inputted to the same input terminal of the voltage boost/buck converter.

Abstract: A projection device includes a casing, a projection lens, a light valve module, a light source module, a first heat dissipation module, a second heat dissipation module, a fan, and a guiding member. The first heat dissipation module is disposed corresponding to a first air inlet of a first side cover and connected to the light valve module, and the second heat dissipation module is disposed corresponding to a second air inlet of a second side cover and connected to the light source module. An airflow in an accommodating space of the casing is guided to the guiding member by the fan, and is transferred from the guiding member to an air outlet to flow out of the casing. A direction of an image beam of the projection lens is different from an airflow direction flowing out from the air outlet of a third side cover.

Abstract: A projection device includes a casing, a light source module, a light valve module, a projection lens, a heat dissipation module, and a fan disposed in the casing. The casing has at least one air inlet, a first air outlet, and a second air outlet. The heat dissipation module is coupled to the light source module and the light valve module and configured to cool the light source module and the light valve module. The fan has a first air exhaust and a second air exhaust. The first air exhaust and the second air exhaust are respectively disposed at positions adjacent to the first air outlet and the second air outlet of the casing.

Abstract: Examples disclosed herein relate to device. The device includes a substrate, a plurality of adjacent pixel-defining layer (PDL structures disposed over the substrate, and a plurality of sub-pixels. The PDL structure have a top surface coupled to adjacent sidewalls of the PDL structure. The plurality of sub-pixels are defined by the PDL structures. Each sub-pixel includes an anode, an organic light emitting diode (OLED), a cathode, and an encapsulation layer. The organic light emitting diode (OLED) material disposed over the anode. The OLED material extends over the top surface of the PDL structure past the adjacent sidewalls. The cathode is disposed over the OLED material. The cathode extends over the top surface of the PDL structure past the adjacent sidewalls. The encapsulation layer is disposed over the cathode. The encapsulation layer has a first sidewall and a second sidewall.

Abstract: A memory address generation device for a test mode comprises row and column address random number counters and a control unit. The row address random number counter receives a counting signal to update a first count value, generates a row address random number based on the first count value, and outputs a row address to the memory. The column address random number counter receives the counting signal to update a second count value, generates a column address random number based on the second count value, and outputs a column address to the memory. The control unit controls the test mode and sets the first/second count value. A difference value between the currently and previously generated row addresses is greater than or equal to 2, and a difference value between the currently and previously generated column addresses is greater than or equal to 2.

Abstract: A system and a method for detecting abnormality of a thin-film deposition process are provided. In the method, a thin-film is deposited on a substrate in a thin-film deposition chamber by using a target, a dimension of a collimator mounted between the target and the substrate is scanned by using at least one sensor disposed in the thin-film deposition chamber to derive an erosion profile of the target, and abnormality of the thin-film deposition process is detected by analyzing the erosion profile with an analysis model trained with data of a plurality of erosion profiles derived under a plurality of deposition conditions.

Abstract: A projection device including a casing, a light source module, an optical engine module and a projection lens is provided. A front cover, a rear cover, a first side cover, a second side cover, an upper cover and a lower cover of the casing surround an accommodating space. The light source module includes a first and a second light sources, and a first and a second light source heat dissipation modules. The lower cover has a first, a second and a third air inlets. The first and the second side covers respectively have a first and a second air outlets. The first and the second light source heat dissipation modules are correspondingly disposed above the first air inlet and correspond to the first air outlet. The second and the third air inlets are respectively disposed below two sides of the projection lens and adjacent to the front cover.

Abstract: A memory stores telemetry data for an information handling system. A processor analyzes applications being executed within the information handling system, and determines one or more of the applications that collect and send the telemetry data. The processor also retrieves a first list of different sets of data to be tracked for each of the applications. Each of the sets of data to be tracked is associated with a different one of the applications. The processor creates a second list of data being logged in the information handling system. Based on the first and second lists, the processor creates a comprehensive list of data tracked by the applications.

Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.

Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.

Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

Abstract: Exfoliated nanoplatelets functionalized with a non-polar moiety, such as an ethylene or propylene derived polymer, are useful for forming composites, films, and polymer blends.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.