Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.

Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.

Abstract: Various embodiments of the present disclosure are directed towards an integrated chip. The integrated chip includes a first photodetector disposed in a first pixel region of a semiconductor substrate and a second photodetector disposed in a second pixel region of the semiconductor substrate. The second photodetector is laterally separated from the first photodetector. A first diffuser is disposed along a back-side of the semiconductor substrate and over the first photodetector. A second diffuser is disposed along the back-side of the semiconductor substrate and over the second photodetector. A first midline of the first pixel region and a second midline of the second pixel region are both disposed laterally between the first diffuser and the second diffuser.

Abstract: A battery pack for an information handling system includes a battery cell configured to provide current to the information handling system, and a battery management unit including an output to the information handling system. The output provides a maximum continuous current (MCC) indication and a peak power (PP) indication. The battery management unit determines an amount of current that the battery cell provides to the information handling system and determines an optimum MCC value that the battery cell can provide to the information handling system. The battery management unit further provides a first value on the PP indication, the first value being greater than the optimum MCC value, sums the amount of current provided to the information handling system that is in excess of the optimum MCC value, determines that the sum is greater than a threshold, and provides a second value on the PP indication, the second value being less than the optimum MCC value.

Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.

Abstract: An adaptor includes non-volatile memory that stores a scan engine. A removable storage device is connected to the adaptor, which in turn is connected to a host computer. Files being copied between the removable storage device and the host computer through the adaptor are scanned for malware using the scan engine.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary semiconductor device comprises a dielectric layer formed over a conductive feature; a semiconductor stack formed over the dielectric layer, wherein the semiconductor stack including semiconductor layers stacked up and separated from each other; a first metal gate structure and a second metal gate structure formed over a channel region of the semiconductor stack, wherein the first metal gate structure and the second metal gate structure wrap each of the semiconductor layers of the semiconductor stack; and a first epitaxial feature disposed between the first metal gate structure and the second metal gate structure over a first source/drain region of the semiconductor stack, wherein the first epitaxial feature extends through the dielectric layer and contacts the conductive feature.

Abstract: Provided is a projection device, including a casing, a light source module, an optical engine module, a projection lens, and a fan. The casing includes a right cover plate and a baffle opposite to each other, and a lower cover plate adjacent to the right cover plate. The baffle divides the casing into first and second areas. The right and lower cover plates respectively have first and second air outlets adjacent to each other and located in the second area. The light source module, the optical engine module, located on a light transmission path of the light source module, the projection lens, connected to the optical engine module, and the fan, adjacent to the baffle, are disposed in the first area of the casing. The projection device is placed in a first or second state, and hot airflow therein flows out from the first or second air outlet.

Abstract: A centrifugal heat dissipation fan including a housing and an impeller disposed in the housing on an axis is provided. The housing has at least one inlet on the axis and has a plurality of outlets in different radial directions. A heat dissipation system of an electronic device is also provided.

Abstract: An electronic transformer includes a first forward rectifier, a second forward rectifier, a third forward rectifier and a backward rectifier. The first forward rectifier is coupled between a first-phase power and a first output terminal. The second forward rectifier is coupled between a second-phase power and the first output terminal. The third forward rectifier is coupled between a third-phase power and the first output terminal. The backward rectifier is coupled between a neutral line and a second output terminal. The first forward rectifier, the second forward rectifier, and the third forward rectifier are configured to half-wave rectify the first-phase power, the second-phase power, and the third-phase power to generate rectified first-phase to third-phase power sources, and superimpose the rectified first-phase to third-phase power sources on the first output end to serve as an output voltage of the electronic transformer.

Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.

Abstract: Embodiments described herein relate to sub-pixel circuits, displays including sub-pixel circuits, and a method of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. Some configurations of the displays described herein, include the sub-pixel circuits and at least one sensor opening adjacent to the overhang structure and an adjacent sub-pixel circuit. The at least one sensor opening includes a sensor disposed thereunder. Other configurations displays described herein, include sub-pixel circuits including OLED sub-pixels and a transparent sub-pixel such that a sensor is disposed thereunder. The configurations described herein utilize sensors that are integrated to increase the transmittance of the display while eliminating the need for bezels and reducing dead zones in the display.

Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.

Abstract: A light source module applicable to a projection device includes a heat dissipation assembly, a first light source, and a second light source. The heat dissipation assembly includes first and second heat dissipation components. The first heat dissipation component includes a first base and a first fin set. The first fin set has a first ventilation surface. The second heat dissipation component includes a second base and a second fin set. The second base has a first surface, a second surface and a ventilation opening. The first surface is opposite to the second surface. The second fin set is arranged on the first surface. The second surface faces the first ventilation surface. The ventilation opening penetrates the first and second surfaces and is aligned with the first ventilation surface. The first light source is arranged on the first base. The second light source is arranged on the second base.

Abstract: The present disclosure provides a method, a system and a kit for assessing the homologous recombination deficiency (HRD) status of a subject. The present disclosure further provides a method, a system and a kit for identifying a treatment based on the HRD status for the human subject.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.