Abstract: Embodiments described herein relate to a device including a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels. Each sub-pixel includes adjacent first overhangs, adjacent second overhangs, an anode, a hole injection layer (HIL) material, an additional organic light emitting diode (OLED) material, and a cathode. Each first overhang is defined by a body structure disposed on and extending laterally past a base structure disposed on the PDL structure. Each second overhang is defined by a top structure disposed on and extending laterally past the body structure. The HIL material is disposed over and in contact with the anode and disposed under the adjacent first overhangs. The additional OLED material is disposed on the HIL material and extends under the first overhang.

Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).

Abstract: Embodiments described herein relate to a device comprising a substrate, a pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality overhang structures. Each overhang structure is defined by a top structure extending laterally past a body structure. Each body structure is disposed over an upper surface of each PDL structure. Overhang structures define a plurality of sub-pixels including a first sub-pixel and a second sub-pixel. Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material, a cathode, and an encapsulation layer. The OLED materials are disposed over the first anode and extends under the overhang structures. The cathodes are disposed over the OLED materials and under the overhang structures. The encapsulation layers are disposed over the first cathode. The first encapsulation layer has a first thickness and the second encapsulation layer has a second thickness different from the first thickness.

Abstract: A lithography exposure system includes a light source, a substrate stage, and a mask stage between the light source and the substrate stage along an optical path from the light source to the substrate stage. The lithography exposure system further comprises a reflector along the optical path. The reflector comprises: a first layer having a first material and a first thickness; a second layer having the first material and a second thickness different from the first thickness; and a third layer between the first layer and the second layer, and having a second material different from the first material.

Abstract: A multi-bit flip-flop includes a first flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The first flip-flop includes a first set pin configured to receive a first set signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second set pin configured to receive the first set signal, and the first set pin and the second set pin are coupled together. The first flip-flop and the second flip-flop are configured to share at least a first clock pin.

Abstract: An integrated circuit includes a first region of the integrated circuit including a first set of pins extending in a first direction, being on a first level, and having a first width in a second direction different from the first direction. The first region has a first height in the second direction. An integrated circuit further includes a second region of the integrated circuit adjacent to the first region, the second region including a second set of pins extending in the first direction, being on a first level, being separated from the first set of pins in the second direction, and having a second width in the second direction, the first width being different from the second width. The second region has a second height in the second direction different from the first height, and the first level is a first metal layer of the integrated circuit.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A semiconductor device including: a first formation site and a second formation site for forming a first conductive bump and a second conductive bump; when a first environmental density corresponding to the first formation site is greater than a second environmental density corresponding to the second formation site, a cross sectional area of the second formation site is greater than a cross sectional area of the first formation site; wherein the first environmental density is determined by a number of formation sites around the first formation site in a predetermined range and the second environmental density is determined by a number of formation sites around the second formation site in the predetermined range; wherein a first area having the first environmental density forms an ellipse layout while a second area having the second environmental density forms a strip layout surrounding the ellipse layout.

Abstract: A sputtering target structure includes a back plate characterized by a first size, and a plurality of sub-targets bonded to the back plate. Each of the sub-targets is characterized by a size that is a fraction of the first size and is equal to or less than a threshold target size. Each sub-target includes a ferromagnetic material containing iron (Fe) and boron (B). Each of the plurality of sub-targets is in direct contact with one or more adjacent sub-targets.

Abstract: A resistor structure includes a resistor body; and a first electrode structure disposed at and being in electric contact with a first end of the resistor body, and a second electrode structure disposed at and being in electric contact with a second end opposite to the first end of the resistor body. Each of the first electrode structure and the second electrode structure has at least one conductive protrusion. The at least one conductive protrusion of the first electrode structure and the at least one conductive protrusion of the second electrode structure both serve as voltage-sensing terminals for electric connection to an external voltage measurement device, or both serve as current-sensing terminals for electric connection to a current measurement device.

Abstract: The present disclosure is directed to a fluid head that is configured to eject a first fluid (e.g., a liquid state fluid) and a second fluid (e.g., a gaseous state fluid). The fluid head is movable in a rotatable-fashion and a translatable-fashion such that the fluid head may be utilized to increase a speed and decrease a period of time for cleaning and drying a workpiece after an electro-chemical polishing (ECP) process or step. The fluid head may also be utilized to increase a speed and decrease a period of time for beveling an edge of a conductive layer on the workpiece. The present disclosure is also directed to methods for cleaning and drying the workpiece as well as beveling the conductive layer of the workpiece utilizing the fluid head.

Abstract: Disclosed are techniques for performing CT beam hardening correction. The CT beam hardening correction includes scanning a phantom to obtain measured projection data of the phantom and calculating corrected projection data of a measured object according to a calculated beam hardening correction factor, measured projection data of the measured object, a corrected projection data of the measured object, and a relationship among expected projection data of a scanned object.

Abstract: A device includes a movable blade having a first surface to receive a semiconductor wafer. The device can include a positional sensor to detect a position of the semiconductor wafer on a surface of the movable blade, relative to a stationary body. The movable blade can be configured to move relative to the stationary body to cause a displacement of the semiconductor wafer relative to the movable blade. The positional sensor can be coupled to the movable blade.

Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.

Abstract: A lithography exposure system includes a light source, a substrate stage, and a mask stage between the light source and the substrate stage along an optical path from the light source to the substrate stage. The lithography exposure system further comprises a reflector along the optical path. The reflector comprises: a first layer having a first material and a first thickness; a second layer having the first material and a second thickness different from the first thickness; and a third layer between the first layer and the second layer, and having a second material different from the first material.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: Embodiments of the present disclosure generally relate to methods for forming an organic light emitting diode (OLED) device. Forming the OLED device comprises depositing a first barrier layer on a substrate having an OLED structure disposed thereon. A first sublayer of a buffer layer is then deposited on the first barrier layer. The first sublayer of the buffer layer is cured with a mixed gas plasma. Curing the first sublayer comprises generating water from the mixed gas plasma in a process chamber in which the curing occurs. The deposition of the first sublayer and the curing of the first sublayer is repeated one or more times to form a completed buffer layer. A second barrier layer is then deposited on the completed buffer layer.

Abstract: A memory address generation device for a test mode comprises row and column address random number counters and a control unit. The row address random number counter receives a counting signal to update a first count value, generates a row address random number based on the first count value, and outputs a row address to the memory. The column address random number counter receives the counting signal to update a second count value, generates a column address random number based on the second count value, and outputs a column address to the memory. The control unit controls the test mode and sets the first/second count value. A difference value between the currently and previously generated row addresses is greater than or equal to 2, and a difference value between the currently and previously generated column addresses is greater than or equal to 2.

Abstract: A device for removing particles in a gas stream includes a first cylindrical portion configured to receive the gas stream containing a target gas and the particles, a rotatable device disposed within the first cylindrical portion and configured to generate a centrifugal force when in a rotational action to divert the particles away from the rotatable device, a second cylindrical portion coupled to the first cylindrical portion and configured to receive the target gas, and a third cylindrical portion coupled to the first cylindrical portion and surrounding the second cylindrical portion, the third cylindrical portion being configured to receive the diverted particles.

Abstract: A method is provided. The method includes forming an interconnect structure electrically connected to a semiconductor device; forming a tantalum-based barrier layer over the interconnect structure; oxidizing the tantalum-based barrier layer to form a tantalum oxide over the tantalum-based barrier layer; and forming a metal layer over the tantalum oxide.