Patents by Inventor Wen Hao

Wen Hao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11949571
    Abstract: A memory stores telemetry data for an information handling system. A processor analyzes applications being executed within the information handling system, and determines one or more of the applications that collect and send the telemetry data. The processor also retrieves a first list of different sets of data to be tracked for each of the applications. Each of the sets of data to be tracked is associated with a different one of the applications. The processor creates a second list of data being logged in the information handling system. Based on the first and second lists, the processor creates a comprehensive list of data tracked by the applications.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: April 2, 2024
    Assignee: Dell Products L.P.
    Inventors: Nikhil M. Vichare, Wen-hao Zeng
  • Patent number: 11942941
    Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: March 26, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Ou, Wen-Hao Chen
  • Publication number: 20240096834
    Abstract: A method is provided. The method includes determining a first bump map indicative of a first set of positions of bumps. The method includes determining, based upon the first bump map, a first plurality of bump densities associated with a plurality of regions of the first bump map. The method includes smoothing the first plurality of bump densities to determine a second plurality of bump densities associated with the plurality of regions of the first bump map. The method includes determining, based upon the second plurality of bump densities, a second bump map indicative of the first set of positions of the bumps and a set of sizes of the bumps.
    Type: Application
    Filed: March 27, 2023
    Publication date: March 21, 2024
    Inventors: Shih Hsuan HSU, Chan-Chung CHENG, Chun-Chen LIU, Cheng-Hung CHEN, Peng-Ren CHEN, Wen-Hao CHENG, Jong-l MOU
  • Patent number: 11934763
    Abstract: A semiconductor device includes a first circuit element, a layer of dielectric material, a first wire and a second wire in the layer of dielectric material, and an array of wires in the layer of dielectric material, wherein a first wire at a first track in the array of wires is electrically connected to the first circuit element, the first wire having a first width, a second wire at a second track in the array of wires has a second width different from the first width, and a third track in the array of wires between the first track and the second track is an empty track, and wherein the first wire is asymmetric with respect to the first track in the array of wires.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 19, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Ou, Wen-Hao Chen
  • Patent number: 11932718
    Abstract: Exfoliated nanoplatelets functionalized with a non-polar moiety, such as an ethylene or propylene derived polymer, are useful for forming composites, films, and polymer blends.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: March 19, 2024
    Assignees: The Texas A&M University System, Formosa Plastics Corporation
    Inventors: Hung-Jue Sue, Joseph Baker, Mingzhen Zhao, Hong-Mao Wu, Wen-Hao Kang, Jen-Long Wu
  • Patent number: 11929434
    Abstract: A switch device includes a P-type substrate, a first gate structure, a first N-well, a shallow trench isolation structure, a first P-well, a second gate structure, a first N-type doped region, a second P-well, and a second N-type doped region. The first N-well is formed in the P-type substrate and partly under the first gate structure. The shallow trench isolation structure is formed in the first N-well and under the first gate structure. The first P-well is formed in the P-type substrate and under the first gate structure. The first N-type doped region is formed in the P-type substrate and between the first gate structure and the second gate structure. The second P-well is formed in the P-type substrate and under the second gate structure. The second N-type doped region is formed in the second P-well and partly under the second gate structure.
    Type: Grant
    Filed: April 15, 2022
    Date of Patent: March 12, 2024
    Assignee: eMemory Technology Inc.
    Inventors: Chih-Hsin Chen, Shih-Chen Wang, Tsung-Mu Lai, Wen-Hao Ching, Chun-Yuan Lo, Wei-Chen Chang
  • Patent number: 11928416
    Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.
    Type: Grant
    Filed: March 1, 2023
    Date of Patent: March 12, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hung-Chih Ou, Kuo-Fu Lee, Wen-Hao Chen, Keh-Jeng Chang, Hsiang-Ho Chang
  • Publication number: 20240076422
    Abstract: A supported metallocene catalyst includes a carrier and a metallocene component. The carrier includes an inorganic oxide particle and an alkyl aluminoxane material. The inorganic oxide particle includes at least one inorganic oxide compound selected from the group consisting of an oxide of Group 3A and an oxide of Group 4A. The alkyl aluminoxane material includes an alkyl aluminoxane compound and an alkyl aluminum compound that is present in amount ranging from greater than 0.01 wt % to less than 14 wt % base on 100 wt % of the alkyl aluminoxane material. The metallocene component is supported on the carrier, and includes one of a metallocene compound containing a metal from Group 3B, a metallocene compound containing a metal from Group 4B, and a combination thereof. A method for preparing the supported metallocene catalyst and a method for preparing polyolefin using the supported metallocene catalyst are also disclosed.
    Type: Application
    Filed: September 1, 2023
    Publication date: March 7, 2024
    Inventors: Jing-Cherng TSAI, Jen-Long WU, Wen-Hao KANG, Kuei-Pin LIN, Jing-Yu LEE, Jun-Ye HONG, Zih-Yu SHIH, Cheng-Hung CHIANG, Gang-Wei SHEN, Yu-Chuan SUNG, Chung-Hua WENG, Hsing-Ya CHEN
  • Patent number: 11920237
    Abstract: The present disclosure provides a multifunction chamber having a multifunctional shutter disk. The shutter disk includes a lamp device, a DC/RF power device, and a gas line on one surface of the shutter disk. With this configuration, simplifying the chamber type is possible as the various specific, dedicated chambers such as a degas chamber, a pre-clean chamber, a CVD/PVD chamber are not required. By using the multifunctional shutter disk, the degassing function and the pre-cleaning function are provided within a single chamber. Accordingly, a separate degas chamber and a pre-clean chamber are no longer required and the overall transfer time between chambers is reduced or eliminated.
    Type: Grant
    Filed: July 20, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wen-Hao Cheng, Yen-Yu Chen, Yi-Ming Dai
  • Patent number: 11921855
    Abstract: An adaptor includes non-volatile memory that stores a scan engine. A removable storage device is connected to the adaptor, which in turn is connected to a host computer. Files being copied between the removable storage device and the host computer through the adaptor are scanned for malware using the scan engine.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: March 5, 2024
    Assignee: TXOne Networks Inc.
    Inventors: Wen-Hao Cheng, Hsiao-Pei Tien, Pao-Han Lee
  • Publication number: 20240071965
    Abstract: A package includes a first package component including a semiconductor die, wherein the semiconductor die includes conductive pads, wherein the semiconductor die is surrounded by an encapsulant; an adaptive interconnect structure on the semiconductor die, wherein the adaptive interconnect structure includes conductive lines, wherein each conductive line physically and electrically contacts a respective conductive pad; and first bond pads, wherein each first bond pad physically and electrically contacts a respective conductive line; and a second package component including an interconnect structure, wherein the interconnect structure includes second bond pads, wherein each second bond pad is directly bonded to a respective first bond pad, wherein each second bond pad is laterally offset from a corresponding conductive pad which is electrically coupled to that second bond pad.
    Type: Application
    Filed: August 29, 2022
    Publication date: February 29, 2024
    Inventors: Tung-Liang Shao, Yu-Sheng Huang, Wen-Hao Cheng, Chen-Hua Yu
  • Patent number: 11914275
    Abstract: Provided is a projection device, including a casing, a light source module, an optical engine module, a projection lens, and a fan. The casing includes a right cover plate and a baffle opposite to each other, and a lower cover plate adjacent to the right cover plate. The baffle divides the casing into first and second areas. The right and lower cover plates respectively have first and second air outlets adjacent to each other and located in the second area. The light source module, the optical engine module, located on a light transmission path of the light source module, the projection lens, connected to the optical engine module, and the fan, adjacent to the baffle, are disposed in the first area of the casing. The projection device is placed in a first or second state, and hot airflow therein flows out from the first or second air outlet.
    Type: Grant
    Filed: July 20, 2021
    Date of Patent: February 27, 2024
    Assignee: Coretronic Corporation
    Inventors: Jui-Cheng Tseng, Wen-Hao Chu
  • Publication number: 20240063297
    Abstract: A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tse-An CHEN, Lain-Jong LI, Wen-Hao CHANG, Chien-Chih TSENG
  • Publication number: 20240063728
    Abstract: An electronic transformer includes a first forward rectifier, a second forward rectifier, a third forward rectifier and a backward rectifier. The first forward rectifier is coupled between a first-phase power and a first output terminal. The second forward rectifier is coupled between a second-phase power and the first output terminal. The third forward rectifier is coupled between a third-phase power and the first output terminal. The backward rectifier is coupled between a neutral line and a second output terminal. The first forward rectifier, the second forward rectifier, and the third forward rectifier are configured to half-wave rectify the first-phase power, the second-phase power, and the third-phase power to generate rectified first-phase to third-phase power sources, and superimpose the rectified first-phase to third-phase power sources on the first output end to serve as an output voltage of the electronic transformer.
    Type: Application
    Filed: November 15, 2022
    Publication date: February 22, 2024
    Inventors: Si-Wei CHEN, Wen-Hao KUO
  • Patent number: 11905964
    Abstract: A fan frame body structure includes a first frame body. The first frame body has a first upper end, a first lower end, a first frame wall and a first main flow way. The first main flow way passes through the first frame body and is formed with a first main inlet and a first main outlet respectively at the first upper end and the first lower end. A first subsidiary flow way is disposed in the first frame wall. The first subsidiary flow way is in parallel the first main flow way. The first subsidiary outlet is positioned at the first upper end of the first frame body in flush with and in adjacency to the first main inlet.
    Type: Grant
    Filed: September 20, 2022
    Date of Patent: February 20, 2024
    Assignee: ASIA VITAL COMPONENTS CO., LTD.
    Inventors: Sung-Wei Sun, Chu-Hsien Chou, Yi-Chih Lin, Pei-Chuan Lee, Wen-Hao Liu
  • Publication number: 20240036449
    Abstract: A light source module applicable to a projection device includes a heat dissipation assembly, a first light source, and a second light source. The heat dissipation assembly includes first and second heat dissipation components. The first heat dissipation component includes a first base and a first fin set. The first fin set has a first ventilation surface. The second heat dissipation component includes a second base and a second fin set. The second base has a first surface, a second surface and a ventilation opening. The first surface is opposite to the second surface. The second fin set is arranged on the first surface. The second surface faces the first ventilation surface. The ventilation opening penetrates the first and second surfaces and is aligned with the first ventilation surface. The first light source is arranged on the first base. The second light source is arranged on the second base.
    Type: Application
    Filed: July 27, 2023
    Publication date: February 1, 2024
    Inventors: WEI-YI LEE, WEN-HAO CHU
  • Publication number: 20240039518
    Abstract: A device including a first supply voltage track, a second supply voltage track, a first reference track, a first standard cell, and a second standard cell. The first supply voltage track is configured to provide a first voltage and the second supply voltage track is configured to provide a second voltage that is greater than the first voltage. The first standard cell is configured to be electrically connected to the first supply voltage track to receive the first voltage and electrically connected to the first reference track. The second standard cell is configured to be electrically connected to the second supply voltage track to receive the second voltage and electrically connected to the first reference track.
    Type: Application
    Filed: July 26, 2022
    Publication date: February 1, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hung-Chih Ou, Wen-Hao Chen
  • Publication number: 20240040831
    Abstract: Embodiments described herein relate to sub-pixel circuits, displays including sub-pixel circuits, and a method of forming sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. Some configurations of the displays described herein, include the sub-pixel circuits and at least one sensor opening adjacent to the overhang structure and an adjacent sub-pixel circuit. The at least one sensor opening includes a sensor disposed thereunder. Other configurations displays described herein, include sub-pixel circuits including OLED sub-pixels and a transparent sub-pixel such that a sensor is disposed thereunder. The configurations described herein utilize sensors that are integrated to increase the transmittance of the display while eliminating the need for bezels and reducing dead zones in the display.
    Type: Application
    Filed: August 1, 2023
    Publication date: February 1, 2024
    Inventors: Chung-chia CHEN, Jungmin LEE, Yu-hsin LIN, Ji Young CHOUNG, Wen-Hao WU, Dieter HAAS, Si Kyoung KIM
  • Publication number: 20240026462
    Abstract: The present disclosure provides a method, a system and a kit for assessing the homologous recombination deficiency (HRD) status of a subject. The present disclosure further provides a method, a system and a kit for identifying a treatment based on the HRD status for the human subject.
    Type: Application
    Filed: August 13, 2021
    Publication date: January 25, 2024
    Inventors: WOEI-FUH WANG, YA-CHI YEH, YING-JA CHEN, SHU-JEN CHEN, CHIEN-HUNG CHEN, KUAN-YING CHEN, WEN-HAO TAN
  • Publication number: 20240020456
    Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect (LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.
    Type: Application
    Filed: July 31, 2023
    Publication date: January 18, 2024
    Inventors: Chun-Yao Ku, Jyun-Hao Chang, Ming-Tao Yu, Wen-Hao Chen