Abstract: A device includes an interconnect structure, a barrier multi-layer structure, an oxide layer, a pad metal layer, and a passivation layer. The barrier multi-layer structure is over the interconnect structure, the barrier multi-layer structure includes a first metal nitride layer and a second metal nitride layer over the first metal nitride layer. The oxide layer is over the barrier multi-layer structure, in which the oxide layer is an oxide of the second metal nitride layer of the barrier multi-layer structure. The pad metal layer is over the oxide layer. The passivation layer is in contact with the barrier multi-layer structure, the oxide layer, and the pad metal layer.

Abstract: The current disclosure describes techniques for managing planarization of features formed on a semiconductor wafer. The disclosed techniques achieve relative planarization of micro bump structures formed on a wafer surface by adjusting the pattern density of the micro bumps formed within various regions on the wafer surface. The surface area size of a micro bump formed within a given wafer surface region may be enlarged or reduced to change the pattern density. A dummy micro bump may be inserted into a given wafer surface region to increase the pattern density.

Abstract: A method and system of processing database transactions in a distributed online transaction processing (OLTP) database is provided. Overhead and network bandwidth associated with a global transaction manager are reduced and scalability improved by determining whether incoming statements are single-shard or multi-shard. For single-shard statements, a local transaction identifier (TXID) stored and associated with a data record reference by the statement is retrieved. The retrieved TXID is compared against a copy of a list of prepared transactions that are pending in a respective data node. If the TXID is in the copy of the prepared list, the statement is caused to await until the previous transaction has been committed or aborted. The visibility of a change committed by the previous is then determined, and the statement is processed.

Abstract: A robot for transferring a wafer is disclosed. A blade of the robot includes a first sensor on an upper surface of the blade and the second sensor on a back surface of the blade. The first sensor is operable to align the blade with a wafer. The second sensor is operable to align the blade with a holder that holds the wafer.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: A method of analyzing a semiconductor wafer includes obtaining a graphic data system (GDS) file corresponding to the semiconductor wafer, using GDS information from the GDS file to provide coordinates of a layout feature of the semiconductor wafer to an electron microscope, using the electron microscope to capture a raw image from the semiconductor wafer based on the coordinates of the layout feature, and performing a measurement operation on the raw image.

Abstract: A method and system of processing database transactions in a distributed online transaction processing (OLTP) database is provided. Overhead and network bandwidth associated with a global transaction manager are reduced and scalability improved by determining whether incoming statements are single-shard or multi-shard. For single-shard statements, a local transaction identifier (TXID) stored and associated with a data record reference by the statement is retrieved. The retrieved TXID is compared against a copy of a list of prepared transactions that are pending in a respective data node. If the TXID is in the copy of the prepared list, the statement is caused to await until the previous transaction has been committed or aborted. The visibility of a change committed by the previous is then determined, and the statement is processed.

Abstract: A method and apparatus for forming an encapsulation layer on an organic light emitting diode (OLED) patterned substrate are described. A sidewall planarization layer fills voids in a scalloped sidewall of a wall feature on the OLED patterned substrate. The sidewall planarization layer is cured in the same chamber as the deposition of the sidewall planarization layer. A barrier layer is formed on the sidewall planarization layer. The sidewall planarization layer provides a planarized surface for good adhesion of the barrier layer over the sidewall planarization layer which minimizes the possibility of defects to the OLED patterned substrate from moisture of oxygen penetrating the OLED patterned substrate.

Abstract: Embodiments described herein relate to a device comprising a substrate, a pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality overhang structures. Each overhang structure is defined by a top structure extending laterally past a body structure. Each body structure is disposed over an upper surface of each PDL structure. Overhang structures define a plurality of sub-pixels including a first sub-pixel and a second sub-pixel. Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material, a cathode, and an encapsulation layer. The OLED materials are disposed over the first anode and extends under the overhang structures. The cathodes are disposed over the OLED materials and under the overhang structures. The encapsulation layers are disposed over the first cathode. The first encapsulation layer has a first thickness and the second encapsulation layer has a second thickness different from the first thickness.

Abstract: An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.

Abstract: A method of forming an integrated circuit includes generating a first and second standard cell layout design, and manufacturing the integrated circuit based on at least the first or second standard cell layout design. The first standard cell layout design has a first height. The second standard cell layout design has a second height different from the first height. The second standard cell layout design is adjacent to the first standard cell layout design. Generating the first standard cell layout design includes generating a first set of pin layout patterns extending in a first direction, being on a first layout level, and having a first width. Generating the second standard cell layout design includes generating a second set of pin layout patterns extending in the first direction, being on the first layout level, and having a second width different from the first width.

Abstract: Embodiments described herein relate to a device including a substrate, a plurality of adjacent pixel-defining layer (PDL) structures disposed over the substrate, and a plurality of sub-pixels. Each sub-pixel includes adjacent first overhangs, adjacent second overhangs, an anode, a hole injection layer (HIL) material, an additional organic light emitting diode (OLED) material, and a cathode. Each first overhang is defined by a body structure disposed over and extending laterally past a base structure disposed over the PDL structure. Each second overhang is defined by a top structure disposed over and extending laterally past the body structure. The HIL material is disposed over and in contact with the anode and disposed under the adjacent first overhangs. The additional OLED material is disposed over the HIL material and extends under the first overhang.

Abstract: A roller type linear guideway includes: a rail, a sliding block sleeved on the rail, and end cover units installed at two ends of the sliding block. One of the end cover units includes a first cover plate, a second cover plate, an open end cover, and an outer end cover. The first cover plate includes a plurality of penetrating holes communicating with the non-load passages, the second cover plate is installed on the first cover plate and includes holes connected to the penetrating holes, and the open end cover is installed on one end of the sliding block and includes through holes communicating with the holes. The outer end cover closes the through holes to allow circulation of multiple rolling elements. The through holes, the holes, and the penetrating holes are connected to the non-load passages, so four rows of rolling elements can be filled simultaneously.

Abstract: A method of process technology assessment is provided. The method includes: defining a scope of the process technology assessment, the scope comprising an original process technology and a first process technology; modeling a first object in an integrated circuit into a resistance domain and a capacitance domain; generating a first resistance scaling factor and a first capacitance scaling factor based on the modeling, the original process technology, and the first process technology; and utilizing, by an electronic design automation (EDA) tool, the first resistance scaling factor and the first capacitance scaling factor for simulation of the integrated circuit.

Abstract: The present disclosure provides a redistribution layer (RDL) structure, a semiconductor device and manufacturing method thereof. The semiconductor device comprising an RDL structure that may include a substrate, a first conductive layer, a reinforcement layer and, and a second conductive layer. The first conductive layer may be formed on the substrate and has a first bond pad area. The reinforcement layer may be formed on a surface of the first conductive layer facing away from the substrate and located in the first bond pad area. The second conductive layer may be formed on the reinforcement layer and an area of the first conductive layer not covered by the reinforcement layer. The reinforcement layer has a material strength greater than those of the first conductive layer and the second conductive layer.

Abstract: The present disclosure provides an integrated circuit (IC) structure. The IC structure includes a semiconductor substrate; an interconnection structure formed on the semiconductor substrate; and a redistribution layer (RDL) metallic feature formed on the interconnection structure. The RDL metallic feature further includes a barrier layer disposed on the interconnection structure; a diffusion layer disposed on the barrier layer, wherein the diffusion layer includes metal and oxygen; and a metallic layer disposed on the diffusion layer.

Abstract: A semiconductor device includes channel region, first and second two-dimensional metallic contacts, a gate structure, and first and second metal contacts. The channel region includes a two-dimensional semiconductor material. The first two-dimensional metallic contact is disposed at a side of the channel region and includes a two-dimensional metallic material. The second two-dimensional metallic contact is disposed at an opposite side of the channel region and includes the two-dimensional metallic material. The gate structure is disposed on the channel region in between the first and second two-dimensional metallic contacts. The first metal contact is disposed at an opposite side of the first two-dimensional metallic contact with respect to the channel region. The second metal contact is disposed at an opposite side of the second two-dimensional metallic contact with respect to the channel region.

Abstract: Systematic fault localization systems and methods are provided which utilize computational GDS-assisted navigation to accelerate physical fault analysis to identify systematic fault locations and patterns. In some embodiments, a method includes detecting a plurality of electrical fault regions of a plurality of dies of a semiconductor wafer. Decomposed Graphic Database System (GDS) cross-layer clips are generated which are associated with the plurality of electrical fault regions. A plurality of cross-layer common patterns is identified based on the decomposed GDS cross-layer clips. Normalized differentials may be determined for each of the cross-layer common patterns, and locations of hotspots in each of the dies may be identified based on the determined normalized differentials.

Abstract: Systems and methods for improving design performance of a layout design through placement of functional and spare cells by leveraging layout dependent effect(LDE) is disclosed. The method includes the steps of: importing a plurality of technology files associated with the layout design into an EDA system; importing a netlist associated with the layout design into the EDA system; importing a standard cell library containing pattern-S timing information of the functional cells and the spare cells; performing floorplan and spare cell insertion, wherein the spare cells are distributed uniformly across the floorplan; and conducting placement and optimization through re-placement of the at least one functional cells and the spare cells to form pattern-S with at least one timing critical cells to improve an overall timing performance of the layout design.

Abstract: Embodiments described herein relate to a device comprising a substrate, a pixel-defining layer (PDL) structures disposed over the substrate and defining sub-pixels of the device, and a plurality overhang structures. Each overhang structure is defined by a top structure extending laterally past a body structure. Each body structure is disposed over an upper surface of each PDL structure. Overhang structures define a plurality of sub-pixels including a first sub-pixel and a second sub-pixel. Each sub-pixel includes an anode, an organic light-emitting diode (OLED) material, a cathode, and an encapsulation layer. The OLED materials are disposed over the first anode and extends under the overhang structures. The cathodes are disposed over the OLED materials and under the overhang structures. The encapsulation layers are disposed over the first cathode. The first encapsulation layer has a first thickness and the second encapsulation layer has a second thickness different from the first thickness.