Abstract: An aggregation node establishes a first session using a traffic-engineering label distribution protocol. The first session has a next hop adjacent to the aggregation node and positioned within a same network as the aggregation node. The aggregation node also establishes a second session using a traffic-engineering label distribution protocol, wherein the second session has a remote next hop positioned at a border between the network and a second network. The aggregation node sends a message destined for the remote next hop over the second session for establishing an end-to-end traffic engineered label switched path for a FEC specified in a label request message received from an access node, wherein the message includes the same the data indicating constraint information that was received by the aggregation node in the label request message.

Abstract: A display panel includes a gate driving circuit and a control circuit. The gate driving circuit includes a plurality of circuit stages. An Nth-circuit stage of the circuit stages includes a start unit, a drive unit, a first pull-down unit, a second pull-down unit, and a current detecting unit. The drive unit is configured to provide a dock signal to an Nth-output terminal. The first pull-down unit is configured to make an enable node have a first pull-down voltage. The second pull-down unit is configured to provide a disable node with a second pull-down voltage. The current detecting unit is configured to detect an error current passing through the first pull-down unit and output an error signal according to the error current. The control circuit is configured to adjust the second pull-down voltage according to the error signal of the Nth-circuit stage.

Abstract: A cover-type containing structure for flexible enclosures primarily includes a front cover sheet, a rear cover sheet and a flexible enclosure. The front cover sheet includes a first joining edge and a cover piece, whereas the rear cover sheet includes a cover assembly corresponding to the cover piece. The flexible enclosure includes a second joining edge and by engaging the first joining edge with the second joining edge, the front cover sheet and the flexible enclosure are fixed. Besides, the containing structure further includes a holding portion. Under a contained state, the holding portion is used to contain smaller objectives; whereas, in an unfolded state, in addition to using the flexible enclosure to contain larger objectives, the holding portion can be also used to contain smaller objectives. The present invention can be also applied to a piece of clothing combined with a bag unit or other flexible enclosure.

Abstract: A push-button structure includes a circuit board, a conductive adhesive mounted on the circuit board, a base column, a splinter and a button body. The base column has an assembling portion. A bottom end of the assembling portion is mounted to the circuit board through the conductive adhesive. The splinter mounted to a top end of the base column has a base plate. Several portions of an outer periphery of the base plate meander outward to form a plurality of elastic arms. A free end of the elastic arm is bent upward to form a fastening piece. The button body has a base portion. Several portions of an outer periphery of the bottom surface of the base portion protrude downward to form a plurality of propping plates. The propping plate hooks a top end of the fastening piece to keep a balance of the button body.

Abstract: A flip-chip light emitting diode, including a substrate, an N-type semiconductor layer, a light emitting layer and a P-type semiconductor layer series mounted along a height direction of the flip-chip light emitting diode. A P electrode is formed on the P-type semiconductor layer and an N electrode is formed on the N-type semiconductor. A top surface of the substrate is away from the light emitting layer. A plurality of micron main portions is formed on the top surface. An outer surface of each main body has a plurality of nanometer protrusions. A method for manufacturing the flip chip light emitting diode is also provided.

Abstract: Disclosed is a liquid crystal compound with negative dielectric anisotropy, having a general formula as Formula 1. In Formula 1, each of L1, L2, L3, and L4, being same or different, is hydrogen, halogen, or cyano group. Each of R1 and R2, being same or different, is hydrogen, halogen, C1-12 alkyl group, C1-12 alkoxy group, C1-12 haloalkyl group, C2-12 alkenyl group, C2-12 ether group, or C2-12 alkynyl group. Each of A1 and A2, being same or different, is benzene, cyclohexane, or cyclohexene. Z1 is —CF2O—, or —OCF2—, and Z2 is —CF2O—, or —OCF2—.

Abstract: The present invention discloses a micro-electro-mechanical system (MEMS) device. The MEMS device includes: a substrate; a proof mass which defines an internal space inside and forms at least two capacitors with the substrate; at least two anchors connected to the substrate and respectively located in the capacitor areas of the capacitors from a cross-sectional view; at least one linkage truss located in the hollow structure, wherein the linkage truss is directly connected to the anchors or indirectly connected to the anchors through buffer springs; and multiple rotation springs located in the hollow structure, wherein the rotation springs are connected between the proof mass and the linkage truss, such that the proof mass can rotate along an axis formed by the rotation springs. There is no coupling mass which does not form a movable electrode in the connection between the proof mass and the substrate.

Abstract: A pixel array includes a substrate and color filter patterns. The substrate has pixel areas. Each of the pixel areas has a first sub-pixel region, a second sub-pixel region, a third sub-pixel region and a fourth sub-pixel region. The first, the second, the third and the fourth sub-pixel regions are arranged sequentially in the clockwise direction. The color filter patterns are disposed on the pixel areas of the substrate and located in the first, the second, the third and the fourth sub-pixel regions. The color filter patterns located in the first, the second, the third and the fourth sub-pixel regions of each of the pixel areas respectively have different colors. The color filter patterns respectively disposed in four adjacent pixel areas and located in the first, the second, the third and the fourth sub-pixel regions adjacent to each other and arranged in the clockwise direction have the same color.

Abstract: The present invention provides a high-voltage metal-oxide-semiconductor (HVMOS) transistor comprising a substrate, a gate dielectric layer, a gate electrode and a source and drain region. The gate dielectric layer is disposed on the substrate and includes a protruded portion and a recessed portion, wherein the protruded portion is disposed adjacent to two sides of the recessed portion and has a thickness greater than a thickness of the recessed portion. The gate electrode is disposed on the gate dielectric layer. Thus, the protruded portion of the gate dielectric layer can maintain a higher breakdown voltage, thereby keeping the current from leaking through the gate.

Abstract: A blender includes a container, a cap, and a sealing module. The cap covers the container. The sealing module includes a mounting seat, a sealing member, a shaft, a valve, and an accessible member. The mounting seat is mounted movably on the cap. The sealing member is disposed in the container, and mounted to the mounting seat. The shaft extends through and is movable relative to the mounting seat, the cap and the sealing member, and has a lower end mounted co-movably to the valve. The accessible member is mounted on the mounting seat, is connected co-movably to the shaft, and is operable to move the shaft along the vertical axis so as to drive the valve between a release position and an air-tight position.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: The invention provides a micro-electro-mechanical system (MEMS) module, which includes a MEMS die stacked on an electronic circuit die. The electronic circuit die includes a substrate, the substrate including at least one through-silicon via (TSV) penetrating through the substrate; and at least one electronic circuit. The electronic circuit includes a circuit region, and a signal transmission layer directly connecting the TSV. At least one wire is connected between a middle part of the MEMS die and the TSV. There is no signal communication at the interfacing location where the MEMS die is stacked on and bonded with the electronic circuit die.

Abstract: A semiconductor structure is provided. The semiconductor structure comprises a substrate, a deep well formed in the substrate, a first well and a second well formed in the deep well, a gate electrode formed on the substrate and disposed between the first well and the second well, a first isolation, and a second isolation. The second well is spaced apart from the first well. The first isolation extends down from the surface of the substrate and is disposed between the gate electrode and the second well. The second isolation extends down from the surface of the substrate and is adjacent to the first well. A ratio of a depth of the first isolation to a depth of the second isolation is smaller than 1.

Abstract: A light emitting diode includes a substrate, an un-doped GaN layer, a plurality of carbon nanotubes, an N-type GaN layer, an active layer formed on the N-type GaN layer, and a P-type GaN layer formed on the active layer. The substrate includes a first surface and a second surface opposite and parallel to the first surface. A plurality of convexes is formed on the first surface of the substrate. The un-doped GaN layer is formed on the first surface of the substrate. The plurality of carbon nanotubes is formed on an upper surface of the un-doped GaN layer. The plurality of carbon nanotubes is spaced from each other to expose a portion of the upper surface of the un-doped GaN layer. The N-type GaN layer is formed on the exposed portion of the upper surface of the un-doped GaN layer and covering the carbon nanotubes therein.

Abstract: The invention relates to an authorizing server, an authorizing method and a computer program product. An authorizing system server is in communication with an electronic device and an agent device. The authorizing server includes a transceiver and a processor. The transceiver receives a request issued by the electronic device. The processor provides an initial authorizing code in response to the request, and generates a server side code accordingly. After transmitting the initial authorizing code, the transceiver receives a remote side code, obtained according to the initial authorizing code. The processor authorizes an operation procedure to be executed when a predetermined condition is satisfied.

Abstract: An engineered epitaxial region compensates for short channel effects of a MOS device by providing a blocking layer to reduce or prevent dopant diffusion while at the same time reducing or eliminating the side effects of the blocking layer such as increased leakage current of a BJT device and/or decreased breakdown voltage of a rectifier. These side effects are reduced or eliminated by a non-conformal dopant-rich layer between the blocking layer and the substrate, which lessens the abruptness of the junction, thus lower the electric field at the junction region. Such a scheme is particularly advantageous for system on chip applications where it is desirable to manufacture MOS, BJT, and rectifier devices simultaneously with common process steps.

Abstract: A combined LED bulb comprises a base body, a light source module detachably arranged at one end of the base body, a light-transmitting hood body detachably covering the same ends of both the base body and the light source module, and a connector detachably connected to the other end of the base body. Through modular design of the elements, the purpose of reducing element, decreasing procedures, improving capacity and yield of finished lamps, and lowering manufacturing cost and labor cost is realized; and the combined light-emitting diode bulb is applicable to a manual production line and an automatic production line at the same time.

Abstract: A copper interconnect includes a copper layer formed in a dielectric layer. A glue layer is formed between the copper layer and the dielectric layer. A barrier layer is formed at the boundary between the glue layer and the dielectric layer. The barrier layer is a metal oxide.

Abstract: A display module is provided. A light source is configured to provide an illumination beam. A light guide plate has a first surface, a second surface opposite to the first surface, and an incident surface connecting the first surface and the second surface. The illumination beam enters the light guide plate through the incident surface. A reflective element is connected to the light guide plate and has a plurality of first reflective surfaces inclined with respect to the second surface. A reflective display unit is capable of modulating a polarization state of the illumination beam to form a modulated beam. The second surface is disposed between the reflective display unit and the first surface. The first surface is disposed between the second surface and a reflective polarizer, and the reflective polarizer filters the modulated beam into an image beam.

Abstract: An apparatus includes a substrate having a strained channel region, a dielectric layer over the channel region, first and second conductive layers over the dielectric layer having a characteristic with a first value, and a strain-inducing conductive layer between the conductive layers having the characteristic with a second value different from the first value. A different aspect involves an apparatus that includes a substrate, first and second projections extending from the substrate, the first projection having a tensile-strained first channel region and the second projection having a compression-strained second channel region, and first and second gate structures engaging the first and second projections, respectively. The first gate structure includes a dielectric layer, first and second conductive layers over the dielectric layer, and a strain-inducing conductive layer between the conductive layers.