Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220359556
    Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 10, 2022
    Applicant: Macronix International Co., Ltd.
    Inventors: TING-FENG LIAO, MAO-YUAN WENG, KUANG-WEN LIU
  • Publication number: 20220352089
    Abstract: A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: HSIEN-WEN LIU, HSIEN-WEI CHEN, JIE CHEN
  • Publication number: 20220352085
    Abstract: A package structure is provided. The package structure includes a first redistribution structure and a second redistribution structure over the first redistribution structure. The package structure also includes. The package structure further includes a semiconductor chip between the first redistribution structure and the second redistribution structure. In addition, the package structure includes a protective layer surrounding the semiconductor chip and a conductive structure penetrating through the protective layer. The conductive structure has a solder element and a conductive pillar, the conductive pillar has a first end and a second end, and the first end is between the second end and the solder element. The solder element has a protruding portion extending from an interface between the conductive pillar and the solder element towards the second end. A terminal of the protruding portion is vertically between the first end and the second end.
    Type: Application
    Filed: July 4, 2022
    Publication date: November 3, 2022
    Inventors: Po-Hao TSAI, Hsien-Wen LIU, Shin-Puu JENG, Meng-Liang LIN, Shih-Yung PENG, Shih-Ting HUNG
  • Publication number: 20220352329
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20220344274
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: July 11, 2022
    Publication date: October 27, 2022
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 11479659
    Abstract: An opaque high-impact methyl methacrylate-butadiene-styrene polymer (MBS) for improving impact resistance of polyvinyl chloride (PVC) including the following components by mass: 80-95% of core layer, 4-20% of shell layer and 0.001-0.05% of protective colloid, where the core layer is a butadiene (B) and styrene (S) polymer, the shell layer is one or a copolymer of two or three of S, acrylate and methyl methacrylate (MMA), and the protective colloid includes one or a compound of two or three of polyvinyl alcohol (PVA), gelatin and hydroxypropylmethyl cellulose (HPMC), may solve the problems of low impact resistance in the existing MBS product and difficult coagulation or spraying in the post-treatment process.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 25, 2022
    Assignee: SHANDONG DONGLIN NEW MATERIALS CO., LTD
    Inventors: Xiaoquan Zhang, Tonggang Yi, Yongquan Xia, Honggang Zhao, Wen Liu, Boxiao Zou, Duo Xu, Xiaomin Ma
  • Patent number: 11482717
    Abstract: A dehydrogenation method for hydrogen storage materials, which is executed by a fuel cell system. The fuel cell system includes a hydrogen storage material tank, a heating unit, a fuel cell, a pump, a water thermal management unit and a heat recovery unit. The described dehydrogenation method utilizes the heating unit and the heat recovery unit to provide thermal energy to the hydrogen storage material tank, so that hydrogen storage material is heated to the dehydrogenation temperature. The pump extracts hydrogen from the hydrogen storage material tank, so that the hydrogen storage material is under negative pressure (i.e. H2 absolute pressure below 1 atm), according to which the hydrogen storage material is dehydrogenated, and the dehydrogenation efficiency and the amount of hydrogen release are improved. The method n can reduce the dehydrogenation temperature of the hydrogen storage material, and reduce the thermal energy consumption for heating the hydrogen storage material.
    Type: Grant
    Filed: March 31, 2021
    Date of Patent: October 25, 2022
    Inventors: Chia-Chieh Shen, Shih-Hung Chan, Fang-Bor Weng, Ho Chun Cheung, Yi-Hsuan Lin, Mei-Chin Chen, Jyun-Wei Chen, Ya-Che Wu, Han-Wen Liu, Kuan-Lin Chen, Jin-Xun Zhang
  • Patent number: 11475009
    Abstract: A database object used in a plurality of database operations is determined. A live range of the database object is computed. The computing of the live range includes determining occurrences of the database operations to the database object. Based at least in part on the live range of the database object, a memory is determined to be optimally assigned to store the database object based on at least one characteristic of the memory. A first time to allocate the database object to the memory is determined. A second time to deallocate the database object from the memory is determined. An output file comprising a first instruction to store the database object in the memory at the first time and a second instruction to deallocate the database object from the memory at the second time is written.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: October 18, 2022
    Assignee: eBay Inc.
    Inventors: Tianyou Li, Wen Liu, Rongguan Fu
  • Publication number: 20220310826
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20220310593
    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. A first fin structure is formed on a substrate. A second fin structure is formed on the substrate. A first semiconductor material is formed on both the first fin structure and the second fin structure. A second semiconductor material is formed on the first semiconductor material on both the first fin structure and the second fin structure. The first semiconductor material on the first fin structure is oxidized to form a first oxide. The second semiconductor material on the first fin structure is removed. A first dielectric material and a first electrode are formed on the first fin structure. A second dielectric material and a second electrode are formed on the second fin structure.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Inventors: Chi-Wen LIU, Chao-Hsiung WANG
  • Patent number: 11456257
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: September 27, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Publication number: 20220302257
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: June 7, 2022
    Publication date: September 22, 2022
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 11437479
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 6, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 11435391
    Abstract: The present disclosure provides a dual-sided wafer imaging apparatus and methods thereof. The dual-sided wafer imaging apparatus includes one or more load ports, one or more mechanical arms for transporting a wafer, a wafer transfer stage, a first line scan camera mounted below the wafer transfer stage, a second line scan camera mounted above the wafer transfer stage, a first optical lens mounted on the first line scan camera, a second optical lens mounted on the second line scan camera, and line light sources respectively mounted below and above the wafer transfer stage. The load ports are configured for an automated load operation or unload operation of a wafer pod of an automated transport equipment. The wafer transfer stage includes vacuum suction points in contact with a backside of the wafer, and the wafer transfer stage further includes a drive motor producing a linear reciprocating motion for moving the wafer.
    Type: Grant
    Filed: January 22, 2020
    Date of Patent: September 6, 2022
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Ying-Chuan Wang, Yi-Wen Liu, Shih-Chih Lin, Jih-Cheng Huang
  • Patent number: 11430739
    Abstract: Structures and formation methods of a package structure are provided. The method includes forming a conductive structure over a carrier substrate and disposing a semiconductor die over the carrier substrate. The method also includes pressing a protective substrate against the carrier substrate at an elevated temperature to bond the protective substrate to the conductive structure. The method further includes forming a protective layer to surround the semiconductor die.
    Type: Grant
    Filed: June 11, 2019
    Date of Patent: August 30, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Hao Tsai, Hsien-Wen Liu, Shin-Puu Jeng, Meng-Liang Lin, Shih-Yung Peng, Shih-Ting Hung
  • Patent number: 11428716
    Abstract: A current detection device including two conductors, a resistor and two detection portions is provided. The resistor is disposed between the two conductors. At least one of the detection portions is a detection terminal including a first terminal portion and a second terminal portion. The first terminal portion includes a first flange and a second flange, the second flange is connected to the second terminal portion, and at least one portion of the second flange is buried into at least one conductor. The first flange is buried into the at least one conductor, a distal end of the first flange does not protrude beyond the second surface, a distance is kept between the distal end of the first flange and the second surface, a gap is defined between the first flange and the second flange, and at least one portion of the gap is filled with a material of the at least one conductor.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: August 30, 2022
    Assignee: CYNTEC CO., LTD.
    Inventor: Po-Wen Liu
  • Publication number: 20220269132
    Abstract: A backlight module includes a light guide plate, a light source, an optical film, and a prism sheet. The optical film includes a first substrate having opposite first and second surfaces and multiple optical microstructures disposed on the second surface and each having a first light receiving surface away from a light incident surface. The prism sheet is located on a side of the second surface of the first substrate. The prism sheet includes a second substrate having opposite third and fourth surfaces and multiple prism structures disposed on the fourth surface and each having a second light receiving surface away from the light incident surface. A first angle between the first light receiving surface and the second surface is different from a second angle between the second light receiving surface and the fourth surface. A display apparatus includes the backlight module and a display panel.
    Type: Application
    Filed: January 26, 2022
    Publication date: August 25, 2022
    Applicant: Nano Precision Taiwan Limited
    Inventors: Kuan-Wen Liu, Hao-Jan Kuo, Ming-Yu Chou, Hsin Huang
  • Publication number: 20220271165
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Application
    Filed: May 13, 2022
    Publication date: August 25, 2022
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Patent number: 11419263
    Abstract: A trimmer head having at least two pivoting line holders for holding multiple folded strips of trimming line is presented wherein said pivoting line holders are retained within said housing between said housing and said cover and extend upward through apertures in said cover, said line holders being capable of movement around a vertical axis of rotation, at least three embodiments are disclosed which provide a rounded landing for supporting the inner radius of a folded strip of trimming line, the rounded geometry of the landing prevents line stress and breakage, the various embodiments include a pivot post having two parallel straight through holes with a rounded vertical wall between the through holes, a single open passageway having a center metal post, and a single open passageway having a series of at least two metal pins through the center of the passageway.
    Type: Grant
    Filed: August 15, 2019
    Date of Patent: August 23, 2022
    Assignee: SHAKESPEARE COMPANY, LLC
    Inventors: David B. Skinner, Brian Searfoss, Wen Liu, Lin Wang, Jack Yang
  • Patent number: 11419852
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: August 23, 2022
    Assignee: GLYCOLYSIS BIOMED CO., LTD.
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao