Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11631768
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: April 18, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai
  • Publication number: 20230092986
    Abstract: An electronic device may include a display and an optical sensor formed underneath the display. A pixel removal region on the display may at least partially overlap with the sensor. The pixel removal region may include a plurality of non-pixel regions each of which is devoid of thin-film transistors. The plurality of non-pixel regions is configured to increase the transmittance of light through the display to the sensor. In addition to removing thin-film transistors in the pixel removal region, additional layers in the display stack-up may be removed. In particular, a cathode layer, polyimide layer, and/or substrate in the display stack-up may be patterned to have an opening in the pixel removal region. A polarizer may be bleached in the pixel removal region for additional transmittance gains. The cathode layer may be removed using laser ablation with a spot laser or blanket illumination.
    Type: Application
    Filed: February 2, 2021
    Publication date: March 23, 2023
    Inventors: Warren S. Rieutort-Louis, Meng-Huan Ho, Abbas Jamshidi Roudbari, Chih Jen Yang, Chin Wei Hsu, Jae Won Choi, Jean-Pierre S. Guillou, Ming Xu, Rui Liu, Yi Qiao, Yu-Wen Liu, Yuchi Che, Yue Cui
  • Publication number: 20230070680
    Abstract: A light guide plate including a light emitting surface, a bottom surface, a light incident surface, multiple protrusion structures, and multiple grooves is provided. The light incident surface is connected between the light emitting surface and the bottom surface. The protrusion structures are disposed along a first direction and extend toward a second direction. The protrusion structures have a light condensing angle along the first direction, and the light condensing angle ranges from 10 degrees to 40 degrees. The grooves are disposed in the protrusion structures of the light guide plate. The grooves extend toward the first direction. The protrusion structures have a light receiving surface that defines each groove and is closer to the light incident surface. An angle between the light receiving surface and the bottom surface ranges from 35 degrees to 65 degrees. A display apparatus adopting the light guide plate is also provided.
    Type: Application
    Filed: August 25, 2022
    Publication date: March 9, 2023
    Applicants: Nano Precision (SuZhou) CO., LTD., Nano Precision Taiwan Limited
    Inventors: Ming-Yu Chou, Hsin Huang, Hao-Jan Kuo, Kuan-Wen Liu, Yun-Chao Chen
  • Patent number: 11594619
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: February 28, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20230056414
    Abstract: A 3D cell culture gel kit and a 3D cell culture method using the same are provided. The 3D cell culture gel kit includes a gel material A, a buffer solution C, and a buffer solution D. The 3D cell culture method includes the steps of adding cells into a mixed solution containing the gel material A and setting the mixed solution at low temperature to get gel containing the cells. Then adding the buffer solution C to the gel for performing crosslinking. Next removing the buffer solution C and adding a growth medium. Let stand until the cells form spheroids in the gel. Moreover, the buffer solution D is used to dissolve the gel and the cells cultured are taken out for analysis. Thereby the 3D cell culture gel kit is convenient to use and suitable for 3D culture of a plurality of cell lines.
    Type: Application
    Filed: August 26, 2020
    Publication date: February 23, 2023
    Inventors: YU-CHUN WU, CHING-WEN LIU, WEI-YU LIN
  • Publication number: 20230051621
    Abstract: A semiconductor structure and a method for manufacturing a semiconductor are provided. The semiconductor structure includes a channel pillar, a dielectric layer formed on the channel pillar, a via formed in the dielectric layer and electrically connected to the channel pillar, and a spacer formed between the dielectric layer and the via.
    Type: Application
    Filed: August 12, 2021
    Publication date: February 16, 2023
    Inventors: Ting-Feng LIAO, Sheng-Hong CHEN, Kuang-Wen LIU
  • Patent number: 11564908
    Abstract: Provided is a long-acting method for preventing or treating glucose metabolism disorders that includes administering a beta-lactam compound or a pharmaceutically acceptable salt thereof to a subject in need thereof. The method for preventing or treating glucose metabolism disorders has a long-acting effect that lasts more than two days even after medication has been stopped.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: January 31, 2023
    Assignee: GLYCOLYSIS BIOMED CO., LTD.
    Inventors: Feng-Ling Lee, Lung-Jr Lin, Jyh-Shing Hsu, Cheng-Hsien Hsu, Yen-Chun Huang, Ya-Chien Huang, Chun-Tsung Lo, Hui-Fang Liao, Yu-Wen Liu, Yu-Chi Kao
  • Publication number: 20230019983
    Abstract: A vacuum cathode arc-induced pulsed thruster includes a housing where a triggering room and an electric discharging room are defined and are in communication with each other, a first anode unit and a first cathode unit concentrically disposed in the triggering room, a second anode unit disposed in the electric discharging room, an insulating fuel layer concentrically located between the first anode unit and the first cathode unit, a main insulating layer concentrically surrounded by the first cathode unit, and a second cathode unit inserted from the triggering room into the electric discharging room. Thus, the vacuum cathode arc-induced pulse thruster is lightweight and has low manufacturing costs, low system complexity, and less energy consumption. Carbon deposition caused during an electric discharging process is prevented from affecting an inducing effect to thereby prolong the service life of the thruster and increase the control precision and inducing precision effectively.
    Type: Application
    Filed: July 13, 2021
    Publication date: January 19, 2023
    Inventors: YUEH-HENG LI, SHENG-WEN LIU, HOU-YI LEE, TIEN-CHUAN KUO, YAO-CHUNG HSU
  • Publication number: 20230004406
    Abstract: An electronic device includes a first graphics processing subsystem, a second graphics processing subsystem, and a screen. The first graphics processing subsystem includes a first application processor, a first graphics processing unit, and a first memory. The second graphics processing subsystem includes a second application processor, a second graphics processing unit, and a second memory. The first graphics processing unit renders a first GUI. The screen displays the first GUI. The second graphics processing unit renders a second GUI, and the second GUI and the first GUI belong to different interface types. The screen displays the second GUI. A display processing method applied to the electronic device is also provided, wherein the first graphics processing subsystem can be switched to the second graphics processing subsystem based on complexity of a to-be-displayed GUI.
    Type: Application
    Filed: November 17, 2020
    Publication date: January 5, 2023
    Inventors: Zhengyuan Hu, Bing Li, Wen Liu, Shuqiang Gong, Zichen Xie
  • Publication number: 20220414123
    Abstract: A categorization system can include a computing device that is configured to obtain a plurality of data items over a threshold analysis period from an incoming data database in response to a threshold analysis interval elapsing. The computing device can also be configured to select a categorization model from a model database. The computing device can also be configured to, for each data item of the plurality of data items, apply the categorization model to the data item to identify at least one topic associated with the corresponding data item. The computing device can also be configured to generate a categorization visualization indicating a frequency of data items corresponding to each topic. The computing device can also be configured to transmit the categorization visualization to at least one of: (i) a user interface of an analyst device and (ii) a categorized database.
    Type: Application
    Filed: June 29, 2021
    Publication date: December 29, 2022
    Inventors: Tolgahan Cakaloglu, Wen Liu, Roshith Raghavan, Srujana Kaddevarmuth
  • Publication number: 20220401575
    Abstract: The presently disclosed subject matter provides a kinetically controlled mixing process, referred to herein as “flash nanocomplexation” or “(FNC),” to accelerate the mixing of a polyanion solution, for example, a plasmid DNA solution, with a polycation solution to match the polyelectrolyte complex (PEC) assembly kinetics through turbulent mixing in a microchamber, thus achieving explicit control of the kinetic conditions for nanoparticle assembly as demonstrated by the tunability of nanoparticle size, composition, hydrodynamic size, hydrodynamic density, surface charge, and polyanion payload.
    Type: Application
    Filed: April 29, 2020
    Publication date: December 22, 2022
    Inventors: Hai-Quan Mao, Yizong Hu, Martin Gilbert Pomper, Heng-wen Liu, Il Minn, Christopher Ullman, Christine Carrington
  • Patent number: 11532524
    Abstract: A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: December 20, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wen Liu, Hsien-Wei Chen
  • Patent number: 11532500
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Patent number: 11523532
    Abstract: An electronic device casing includes a body, a movable apparatus, and a handle structure. The body comprises a first stopping surface and a second stopping surface disposed opposite to each other. The movable apparatus is adapted to be detachably assembled in the body. The handle structure is pivotally disposed to the movable apparatus. The handle structure comprises a first arm corresponding to the first stopping surface and a second arm corresponding to the second stopping surface. The movable apparatus is adapted to move between a removed position and an assembled position by rotating the handle structure between an upper pulled position and a lower pressed position.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: December 6, 2022
    Assignee: PEGATRON CORPORATION
    Inventor: Yu-Wen Liu
  • Publication number: 20220375843
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Application
    Filed: August 5, 2022
    Publication date: November 24, 2022
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Publication number: 20220367296
    Abstract: A semiconductor device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer. The conductive pad is between the interconnect layer and the conductive seed layer.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Inventors: Hsien-Wen Liu, Hsien-Wei Chen
  • Publication number: 20220359556
    Abstract: Methods, systems and apparatus for memory devices with multiple string select line (SSL) cuts are provided. In one aspect, a semiconductor device includes: a three-dimensional (3D) array of memory cells and a plurality of common source lines (CSLs) configured to separate the 3D array of memory cells into a plurality of portions. Each portion of the plurality of portions is between two adjacent CSLs and includes a plurality of conductive layers separated from each other by insulating layers and a plurality of vertical channels arranged orthogonally through the plurality of conductive layers and the insulating layers, each of the plurality of vertical channels including a string of memory cells. A top part of each portion of one or more portions includes at least two SSL cuts configured to separate the portion into multiple independent units, and each of the independent units is selectable by a corresponding SSL of multiple SSLs.
    Type: Application
    Filed: May 7, 2021
    Publication date: November 10, 2022
    Applicant: Macronix International Co., Ltd.
    Inventors: TING-FENG LIAO, MAO-YUAN WENG, KUANG-WEN LIU
  • Publication number: 20220359754
    Abstract: A method of fabrication of a multi-gate semiconductor device that includes providing a fin having a plurality of a first type of epitaxial layers and a plurality of a second type of epitaxial layers. The plurality of the second type of epitaxial layers is oxidized in the source/drain region. A first portion of a first layer of the second type of epitaxial layers is removed in a channel region of the fin to form an opening between a first layer of the first type of epitaxial layer and a second layer of the first type of epitaxial layer. A portion of a gate structure is then formed in the opening.
    Type: Application
    Filed: July 15, 2022
    Publication date: November 10, 2022
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Publication number: 20220352089
    Abstract: A semiconductor structure includes a first die having a first surface and a second surface opposite to the first surface, a conductive bump disposed at the first surface, and an RDL under the conductive bump. The RDL includes an interconnect structure and a dielectric layer, and the interconnect structure is electrically connected to the first die through the conductive bump. The semiconductor structure further includes a molding over the RDL and surrounding the first die and the conductive bump, an adhesive over the molding and the second surface, and a support element over the adhesive. A method includes providing a first die having a first surface and a second surface, a redistribution layer over the first surface, and a molding surrounding the first die; removing a portion of the molding to expose the second surface; and attaching a support element over the molding and the second surface.
    Type: Application
    Filed: April 29, 2021
    Publication date: November 3, 2022
    Inventors: HSIEN-WEN LIU, HSIEN-WEI CHEN, JIE CHEN
  • Publication number: 20220352329
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: July 18, 2022
    Publication date: November 3, 2022
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung