Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: A shuttered keystone jack assembly is provided in the disclosure. The shutter keystone jack assembly includes a jack housing, a frame, a shutter and an elastic member. The frame is detachably disposed on the jack housing and defining a receiving opening. The shutter is pivotally connected to the frame and selectively covering the receiving opening. The elastic member includes a first end portion and a second end portion, and the first end portion and the second end portion respectively abut against the frame and the shutter.

Abstract: A fluorescence image registration method includes obtaining at least one fluorescence image of a biochip. An interior local area. Sums of pixel values in the interior local area along a first direction and a second direction are obtained. A plurality of first template lines is selected to find a minimum total value of the sums of pixel values corresponding to the first template lines. Pixel-level correction is performed on a local area of the track line to obtain a pixel-level track cross. Other track crosses on the biochip is obtained, and the pixel-level correction is performed on the other track crosses. The position of the pixel-level track line is corrected by a center-of-gravity method to obtain the subpixel-level position of the track line. The subpixel-level positions of all sites uniformly distributed on the biochip is obtained.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Abstract: The present disclosure relates to a field of construction engineering, and in particular to a reinforcing structure of a concrete overhead layer before a building expires. The reinforcing structure of the concrete overhead layer includes supporting structures, connecting structures, and metal members; wherein the reinforcing structure is configured to reinforce a concrete floor slab and/or a concrete beam; through holes are disposed on the concrete floor slab; each of the supporting structures passes through each of the through holes and the supporting structures are configured to support the concrete floor slab and/or the concrete beam; and each of the connecting structures is configured to fix each of the supporting structures on each of the metal members; each of the metal members is disposed on each of the through holes.

Abstract: The presently described compounds relate to the treatment of Type I and/or Type II diabetes and/or hyperglycemia. More particularly, the described compounds relate to extended time action acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A profile download method includes a primary device obtaining an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID. The primary device receives the profile download information from the mobile operator server and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and where the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: Traffic jam patterns can be identified and, based on historical traffic data, pre-traffic jam patterns that are likely to result in the traffic jam patterns can be identified as well. Real-time traffic data regarding a driving road of a community can be received and analyzed to determine whether the real-time traffic data match with a pre-traffic jam pattern. If the data matches a pre-traffic jam pattern, an alerting signal for predicting a traffic jam can be transmitted.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region includes a plurality of complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an insulating layer on the N-type doped poly silicon layer; and a P-type doped poly silicon layer on the insulating layer. The array region includes a plurality of gate structures and a plurality of oxide layers alternately stacked on the P-type doped poly silicon layer, wherein a bottommost gate structure of the gate structures and the P-type doped poly silicon layer together serve as a plurality ground select lines of the semiconductor device. The array region further includes a vertical channel structure penetrating the gate structures and the oxide layers and extending into the N-type doped poly silicon layer.

Abstract: A vacuum cathode arc-induced pulsed thruster includes a housing where a triggering room and an electric discharging room are defined and are in communication with each other, a first anode unit and a first cathode unit concentrically disposed in the triggering room, a second anode unit disposed in the electric discharging room, an insulating fuel layer concentrically located between the first anode unit and the first cathode unit, a main insulating layer concentrically surrounded by the first cathode unit, and a second cathode unit inserted from the triggering room into the electric discharging room. Thus, the vacuum cathode arc-induced pulse thruster is lightweight and has low manufacturing costs, low system complexity, and less energy consumption. Carbon deposition caused during an electric discharging process is prevented from affecting an inducing effect to thereby prolong the service life of the thruster and increase the control precision and inducing precision effectively.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: An electronic device may include a display and an optical sensor formed underneath the display. A pixel removal region on the display may at least partially overlap with the sensor. The pixel removal region may include a plurality of non-pixel regions each of which is devoid of thin-film transistors. The plurality of non-pixel regions is configured to increase the transmittance of light through the display to the sensor. In addition to removing thin-film transistors in the pixel removal region, additional layers in the display stack-up may be removed. In particular, a cathode layer, polyimide layer, and/or substrate in the display stack-up may be patterned to have an opening in the pixel removal region. A polarizer may be bleached in the pixel removal region for additional transmittance gains. The cathode layer may be removed using laser ablation with a spot laser or blanket illumination.

Abstract: A light guide plate including a light emitting surface, a bottom surface, a light incident surface, multiple protrusion structures, and multiple grooves is provided. The light incident surface is connected between the light emitting surface and the bottom surface. The protrusion structures are disposed along a first direction and extend toward a second direction. The protrusion structures have a light condensing angle along the first direction, and the light condensing angle ranges from 10 degrees to 40 degrees. The grooves are disposed in the protrusion structures of the light guide plate. The grooves extend toward the first direction. The protrusion structures have a light receiving surface that defines each groove and is closer to the light incident surface. An angle between the light receiving surface and the bottom surface ranges from 35 degrees to 65 degrees. A display apparatus adopting the light guide plate is also provided.