Abstract: A method and a kit for evaluating the risk of diseases or conditions associated with atherosclerosis by detecting at least one genotype for single nucleotide polymorphism in a biological sample of a subject. The at least one genotype for the single nucleotide polymorphism may be a genotype for rs12657663 in CAMLG gene, a genotype for rs2273970 in GALNT2 gene, a genotype for rs643634 in SPINDOC gene, a genotype for rs737976 in THOC5 gene, or a genotype for rs9988179 in SAMD11 gene.

Abstract: A light-emitting device includes a semiconductor epitaxial structure that has a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a first mesa side wall that is defined by a side wall of the first conductive semiconductor layer and a side wall of the active layer, and a first mesa surface that is defined by a portion of a top surface of the second conductive semiconductor layer. The first mesa side wall has a side wall bottom end connected to the first mesa surface to form a connection portion, which is constituted of the side wall bottom end and a mesa surface proximal region of the first mesa surface that adjoins the side wall bottom end and is roughened. A method for manufacturing the light-emitting device is also disclosed.

Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

Abstract: An electronic package is provided, which includes a substrate structure and an electronic element and a passive element disposed on the substrate structure, where a die placement area and a functional area separated from each other are defined on a surface of a substrate body of the substrate structure, so that a routing layer is arranged with linear conductive traces with a smaller width in the die placement area, and a sheet-shaped circuit with a larger width and electrically connected to the linear conductive traces is arranged in the functional area, so as to reduce a metal area on the surface of the substrate body, thereby avoiding the problem of warpage caused by stress concentration in the die placement area.

Abstract: A backlight module includes a light guide plate, a light source, an optical film, and a prism sheet. The optical film includes a first substrate having opposite first and second surfaces and multiple optical microstructures disposed on the second surface and each having a first light receiving surface away from a light incident surface. The prism sheet is located on a side of the second surface of the first substrate. The prism sheet includes a second substrate having opposite third and fourth surfaces and multiple prism structures disposed on the fourth surface and each having a second light receiving surface away from the light incident surface. A first angle between the first light receiving surface and the second surface is different from a second angle between the second light receiving surface and the fourth surface. A display apparatus includes the backlight module and a display panel.

Abstract: A composite material structure includes a first metal member and a second metal member bonding to the first metal member. A bonding surface is formed therebetween. A first hole is through the first metal member. A circular bonding line is formed at a junction of a wall of the first hole and the bonding surface. A sleeve protrudes from the second metal member into the first hole, and covers the bonding line. A groove indents from the first metal member. The groove has a bottom surface located in the same plane with a top surface of the sleeve. A processing method of the composite material structure is also provided. The sleeve covers the bonding line between the first metal member and the second metal member, which allows the composite material structure to provide an improved sealing performance.

Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.

Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.

Abstract: A shuttered keystone jack assembly is provided in the disclosure. The shutter keystone jack assembly includes a jack housing, a frame, a shutter and an elastic member. The frame is detachably disposed on the jack housing and defining a receiving opening. The shutter is pivotally connected to the frame and selectively covering the receiving opening. The elastic member includes a first end portion and a second end portion, and the first end portion and the second end portion respectively abut against the frame and the shutter.

Abstract: A fluorescence image registration method includes obtaining at least one fluorescence image of a biochip. An interior local area. Sums of pixel values in the interior local area along a first direction and a second direction are obtained. A plurality of first template lines is selected to find a minimum total value of the sums of pixel values corresponding to the first template lines. Pixel-level correction is performed on a local area of the track line to obtain a pixel-level track cross. Other track crosses on the biochip is obtained, and the pixel-level correction is performed on the other track crosses. The position of the pixel-level track line is corrected by a center-of-gravity method to obtain the subpixel-level position of the track line. The subpixel-level positions of all sites uniformly distributed on the biochip is obtained.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Abstract: The present disclosure relates to a field of construction engineering, and in particular to a reinforcing structure of a concrete overhead layer before a building expires. The reinforcing structure of the concrete overhead layer includes supporting structures, connecting structures, and metal members; wherein the reinforcing structure is configured to reinforce a concrete floor slab and/or a concrete beam; through holes are disposed on the concrete floor slab; each of the supporting structures passes through each of the through holes and the supporting structures are configured to support the concrete floor slab and/or the concrete beam; and each of the connecting structures is configured to fix each of the supporting structures on each of the metal members; each of the metal members is disposed on each of the through holes.

Abstract: The presently described compounds relate to the treatment of Type I and/or Type II diabetes and/or hyperglycemia. More particularly, the described compounds relate to extended time action acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A profile download method includes a primary device obtaining an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID. The primary device receives the profile download information from the mobile operator server and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and where the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: A semiconductor device includes a peripheral circuit region, a substrate on the peripheral circuit region, and an array region on the substrate. The peripheral circuit region has complementary metal-oxide-semiconductor components. The substrate includes an N-type doped poly silicon layer on the peripheral circuit region, an oxide layer on the N-type doped poly silicon layer, and a conductive layer on the oxide layer. The array region includes gate structures and insulating layers alternately stacked on the conductive layer. A bottommost gate structure and the conductive layer together serve as ground select lines of the semiconductor device, and a ratio of a thickness of the conductive layer to a thickness of each of the gate structures is about 3 to 4. The array region further includes a vertical channel structure penetrating the gate structures and the insulating layers and extending into the N-type doped poly silicon layer.

Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material may be be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.

Abstract: Traffic jam patterns can be identified and, based on historical traffic data, pre-traffic jam patterns that are likely to result in the traffic jam patterns can be identified as well. Real-time traffic data regarding a driving road of a community can be received and analyzed to determine whether the real-time traffic data match with a pre-traffic jam pattern. If the data matches a pre-traffic jam pattern, an alerting signal for predicting a traffic jam can be transmitted.