Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a stack, active structures connecting structures and isolation layers. The stack is disposed on the substrate. The active structures penetrate through the stack in sub-array regions thereof. A plurality of memory cells are defined by cross points of gate electrodes in the stack and the active structures. The connecting structures penetrate through the stack between the sub-array regions. Each connecting structure includes a first portion, a second portion and a third portion. The first portion is formed as an outermost layer of the connecting structure and formed of polysilicon. The second portion is disposed in a space defined by the first portion and formed of amorphous silicon. The third portion is disposed on the second portion and formed of amorphous silicon. The isolation layers are disposed between sidewalls of the stack and the connecting structures.

Abstract: A network communication device having an antenna frame includes a circuit board, a network communication chip, an antenna, a signal cable and an antenna frame. The network communication chip is disposed on the circuit board. The signal cable is electrically connected to the antenna and the circuit board. The antenna frame is assembled on the circuit board. The antenna frame has a slot. The antenna is engaged in the slot. The antenna is directly fixed on the circuit board through the antenna frame, and the assembling of the antenna is easy to complete.

Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: A fluorescence image registration method includes obtaining at least one fluorescence image of a biochip. An interior local area is selected. Sums of pixel values in the interior local area along a first direction and a second direction are obtained. A plurality of first template lines is selected to find a minimum total value of the sums of pixel values corresponding to the first template lines. Pixel-level correction is performed on a local area of the track line to obtain pixel-level track cross. Other track crosses on the biochip is obtained, and the pixel-level correction is performed on the other track crosses. The position of the pixel-level track line is corrected by a center-of-gravity method to obtain the subpixel-level position of the track line. The subpixel-level positions of all sites uniformly distributed on the biochip is obtained.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: The invention provides a radio frequency (RF) module and associated method with envelope tracking (ET) power supply in a device. The RF module may comprise a plurality of transmitters, an ET output, and an ET multiplexer. Each said transmitter may comprise an ET port and one or more RF outputs, and may be configured for providing an RF signal to one of said one or more RF outputs, and providing an ET signal, which reflects an envelope of the RF signal, to the ET port. The ET multiplexer may be coupled between said ET ports of the plurality of transmitters and the ET output, for selectively relaying one of said ET ports to the ET output.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a conductive pillar having a sidewall and a multi-layer isolation structure on the sidewall of the conductive pillar. The multi-layer isolation structure includes a first isolation layer and a second isolation layer. The first isolation layer is between the conductive pillar and the second isolation layer. The first isolation layer includes protrusions extending toward the second isolation layer. A density of the first isolation layer is different from that of the second isolation layer.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.

Abstract: A transmission rate management method is provided. The transmission rate management method is applied to a transmission rate management device. The transmission rate management method includes the steps of calculating a total available data traffic of the transmission rate management device based on a data plan for the transmission rate management device, wherein the total available data traffic corresponds to a period of time; allocating to each of one or more client devices currently connected to the transmission rate management device one available data traffic corresponding to the period of time according to the total available data traffic; and adjusting a transmission rate of a client device of the one or more client devices based on a remaining data traffic of the available data traffic of the client device.

Abstract: A light-emitting device includes a semiconductor epitaxial structure that has a first conductive semiconductor layer, a second conductive semiconductor layer, and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, a first mesa side wall that is defined by a side wall of the first conductive semiconductor layer and a side wall of the active layer, and a first mesa surface that is defined by a portion of a top surface of the second conductive semiconductor layer. The first mesa side wall has a side wall bottom end connected to the first mesa surface to form a connection portion, which is constituted of the side wall bottom end and a mesa surface proximal region of the first mesa surface that adjoins the side wall bottom end and is roughened. A method for manufacturing the light-emitting device is also disclosed.

Abstract: A method and a kit for evaluating the risk of diseases or conditions associated with atherosclerosis by detecting at least one genotype for single nucleotide polymorphism in a biological sample of a subject. The at least one genotype for the single nucleotide polymorphism may be a genotype for rs12657663 in CAMLG gene, a genotype for rs2273970 in GALNT2 gene, a genotype for rs643634 in SPINDOC gene, a genotype for rs737976 in THOC5 gene, or a genotype for rs9988179 in SAMD11 gene.

Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

Abstract: An electronic package is provided, which includes a substrate structure and an electronic element and a passive element disposed on the substrate structure, where a die placement area and a functional area separated from each other are defined on a surface of a substrate body of the substrate structure, so that a routing layer is arranged with linear conductive traces with a smaller width in the die placement area, and a sheet-shaped circuit with a larger width and electrically connected to the linear conductive traces is arranged in the functional area, so as to reduce a metal area on the surface of the substrate body, thereby avoiding the problem of warpage caused by stress concentration in the die placement area.

Abstract: A backlight module includes a light guide plate, a light source, an optical film, and a prism sheet. The optical film includes a first substrate having opposite first and second surfaces and multiple optical microstructures disposed on the second surface and each having a first light receiving surface away from a light incident surface. The prism sheet is located on a side of the second surface of the first substrate. The prism sheet includes a second substrate having opposite third and fourth surfaces and multiple prism structures disposed on the fourth surface and each having a second light receiving surface away from the light incident surface. A first angle between the first light receiving surface and the second surface is different from a second angle between the second light receiving surface and the fourth surface. A display apparatus includes the backlight module and a display panel.

Abstract: A composite material structure includes a first metal member and a second metal member bonding to the first metal member. A bonding surface is formed therebetween. A first hole is through the first metal member. A circular bonding line is formed at a junction of a wall of the first hole and the bonding surface. A sleeve protrudes from the second metal member into the first hole, and covers the bonding line. A groove indents from the first metal member. The groove has a bottom surface located in the same plane with a top surface of the sleeve. A processing method of the composite material structure is also provided. The sleeve covers the bonding line between the first metal member and the second metal member, which allows the composite material structure to provide an improved sealing performance.