Abstract: A touch display and method for controlling the same are provided. The touch display includes a gate driver circuit, a touch sensor and a display panel. The method includes: when the touch sensor detects no touch input signal, the gate driver circuit outputs a plurality of first gate signals to the display panel at a first frequency; and when the touch sensor detects a touch input signal, the gate driver circuit outputs a plurality of second gate signals to the display panel at a second frequency. The second frequency is smaller than the first frequency.

Abstract: A device includes a semiconductor die. The semiconductor die includes a device layer, an interconnect layer over the device layer, a conductive pad over the interconnect layer, a conductive seed layer directly on the conductive pad, and a passivation layer encapsulating the conductive pad and the conductive seed layer.

Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.

Abstract: A semiconductor structure and a method for manufacturing the same are provided. The semiconductor structure includes a source line structure. The source line structure includes a composite material formed in a trench. The composite material includes an oxide portion and a metal portion.

Abstract: A profile download method includes a primary device obtaining an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID. The primary device receives the profile download information from the mobile operator server and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and where the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.

Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.

Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: A semiconductor device assembly includes a first remote distribution layer (RDL), the first RDL comprising a lower outermost planar surface of the semiconductor device assembly; a first semiconductor die directly coupled to an upper surface of the first RDL by a first plurality of interconnects; a second RDL, the second RDL comprising an upper outermost planar surface of the semiconductor device assembly opposite the lower outermost planar surface; a second semiconductor die directly coupled to a lower surface of the second RDL by a second plurality of interconnects; an encapsulant material disposed between the first RDL and the second RDL and at least partially encapsulating the first and second semiconductor dies; and a third plurality of interconnects extending fully between and directly coupling the upper surface of the first RDL and the lower surface of the second RDL.

Abstract: The present invention discloses an easy-to-process, opaque and high-impact methyl methacrylate-butadiene-styrene (MBS) polymer for polyvinyl chloride (PVC) and a preparation method thereof, and relates to the technical field of preparation of PVC additives. The easy-to-process, opaque and high-impact MBS for PVC has a core-kernel-shell (three-layer) structure, and includes the following components by mass: 1-20% of core, 70-85% of kernel and 5-20% of shell. The core is a semi-hard, lightly crosslinked copolymer of a styrene (St) monomer and an acrylate monomer. The kernel is a soft, lightly crosslinked butadiene (BD)-St polymer with a low glass transition temperature. The shell is a copolymer of St, butyl acrylate and methyl methacrylate (MMA) with a high glass transition temperature. The present invention solves the problems of low impact strength and poor processing fluidity of the existing MBS for opaque PVC products.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: Intelligent multi-scale image parsing determines the optimal size of each observation by an artificial agent at a given point in time while searching for the anatomical landmark. The artificial agent begins searching image data with a coarse field-of-view and iteratively decreases the field-of-view to locate the anatomical landmark. After searching at a coarse field-of view, the artificial agent increases resolution to a finer field-of-view to analyze context and appearance factors to converge on the anatomical landmark. The artificial agent determines applicable context and appearance factors at each effective scale.

Abstract: The present disclosure relates to a field of construction engineering, and in particular to a reinforcing structure of a concrete overhead layer before a building expires. The reinforcing structure of the concrete overhead layer includes supporting structures, connecting structures, and metal members; wherein the reinforcing structure is configured to reinforce a concrete floor slab and/or a concrete beam; through holes are disposed on the concrete floor slab; each of the supporting structures passes through each of the through holes and the supporting structures are configured to support the concrete floor slab and/or the concrete beam; and each of the connecting structures is configured to fix each of the supporting structures on each of the metal members; each of the metal members is disposed on each of the through holes.

Abstract: A semiconductor device includes a substrate, a stacked structure disposed on the substrate, and dummy memory string structures. The stacked structure includes alternately stacked insulating layers and conductive layers. The dummy memory string structures disposed in a staircase region of the semiconductor device penetrate the stacked structure along a first direction. The staircase region includes a body portion including a first region and a second region adjacent to the first region. In the first region, an amount of conductive layers corresponding to the dummy memory string structures is between 1 and 10; in the second region, an amount of conductive layers corresponding to the dummy memory string structures is greater than 10. An area of the dummy memory string structures in the first region is greater than an area of the dummy memory string structures in the second area under an identical unit area in a top view.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, a plurality of conductive structures, an encapsulant, and a second redistribution structure. The die is bonded to the first redistribution structure through flip-chip bonding. The conductive structures surround the die. The encapsulant encapsulates the die and the conductive structures. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant. Top surfaces of the conductive structures contacting the second redistribution structure are coplanar with a top surface of the encapsulant.

Abstract: A device includes a substrate including a low-resistance top surface and a fin structure including a first fin and a second fin. Each of the first and second fins includes a low-resistance fin-top surface and two low-resistance sidewall surfaces. The device includes an insulation material over the top surface of the substrate and between the first fin and the second fin. The fin-top surface and a first portion of the sidewall surfaces of each of the first and the second fins are above the insulation material. The device further includes a dielectric layer over the insulation material and in direct contact with the fin-top surface and the first portion of the sidewall surfaces of each of the first and the second fins; a first electrode in direct contact with the fin-top surface of the first fin; and a second electrode over the dielectric layer that is over the second fin.

Abstract: A chip packaging structure includes a heat dissipation substrate, a pre-molded chipset, an interconnection and a second encapsulant. The pre-molded chipset is located on the heat dissipation substrate. The interconnection is located in the packaging structure and electrically connects the heat dissipation substrate and the pre-molded chipset. The second encapsulant covers part of the heat dissipation substrate, part or all of the interconnection, and part or all of the pre-molded chipset. The pre-molded chipset includes a thermally conductive substrate, at least two chips, a patterned circuit, and a first encapsulant. The patterned circuit is located in the pre-molded chipset. At least two chips are electrically connected by the patterned circuit. The first encapsulant covers at least two chips and part or all of the patterned circuit. A manufacturing method of a chip packaging structure is also provided.

Abstract: Asphalt emulsions, methods of forming asphalt emulsions, and composite pavement structures formed from the asphalt emulsions are provided herein. In an embodiment, an asphalt emulsion includes a base asphalt component, water, and an oxidized high density polyethylene. The base asphalt component is present in an amount of from about 15 to about 70 weight %, the water is present in an amount of at least about 25 weight %, and the oxidized high density polyethylene is present in an amount of from about 1 to about 20 weight %, where all amounts are based on the total weight of the asphalt emulsion. The oxidized high density polyethylene has an acid value of from about 5 to about 50 mgKOH/g. The asphalt emulsion is free of aggregate and other mineral materials.