Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor device and fabricating method thereof
    Patent number: 11018131
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • HANDLE EXTENSION STRUCTURE AND ELECTRONIC DEVICE CASING
    Publication number: 20210153368
    Abstract: A handle extension structure includes a connection assembly and an operation assembly. The connection assembly has a first end and a second end opposite to each other. The operation assembly is slidably disposed at the connection assembly. The operation assembly includes an extension element and a grip element. The extension element has a first end portion and a second end portion opposite to each other. The first end portion is slidably disposed between the first end and the second end. The grip element is pivoted to the second end portion. An electronic device casing includes a body, a movable apparatus, and the handle extension structure. The handle extension structure is pivoted to the movable apparatus through the connection assembly.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 20, 2021
    Applicant: PEGATRON CORPORATION
    Inventors: Long-Sing Ye, Yao-Hsien Huang, Yu-Wen Liu
  • ELECTRONIC DEVICE CASING
    Publication number: 20210153371
    Abstract: An electronic device casing includes a body, a movable apparatus, and a handle structure. The body comprises a first stopping surface and a second stopping surface disposed opposite to each other. The movable apparatus is adapted to be detachably assembled in the body. The handle structure is pivotally disposed to the movable apparatus. The handle structure comprises a first arm corresponding to the first stopping surface and a second arm corresponding to the second stopping surface. The movable apparatus is adapted to move between a removed position and an assembled position by rotating the handle structure between an upper pulled position and a lower pressed position.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 20, 2021
    Applicant: PEGATRON CORPORATION
    Inventor: Yu-Wen Liu
  • Smart phone with a text recognition module
    Patent number: 11012549
    Abstract: A portable device can transmit information through one of a mobile phone network and an Internet, wherein the portable device includes a text-based communication module to allow a user may synchronously transmit or receive data through a local area network, wherein the data is text, audio, video or the combination thereof. The text-based communication module of the portable device includes a text-to-speech recognition module used to convert a text data for outputting the text data by vocal, and a read determination module for determining read target terminals and unread target terminals when a user of the portable phone device activates the read determination module.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: May 18, 2021
    Inventors: Chi-Wen Liu, Ching-Yu Chang, Kuo-Ching Chiang
  • SPEECH SYNTHESIS SYSTEM, METHOD AND NON-TRANSITORY COMPUTER READABLE MEDIUM
    Publication number: 20210142784
    Abstract: A speech synthesis system includes an operating interface, a storage unit and a processor. The operating interface provides a plurality of language options for a user to select one output language option therefrom. The storage unit stores a plurality of acoustic models. Each acoustic model corresponds to one of the language options and includes a plurality of phoneme labels corresponding to a specific vocal. The processor receives a text file and generates output speech data corresponding to the specific vocal according to the text file, a speech synthesizer, and one of the acoustic models which corresponds to the output language option.
    Type: Application
    Filed: December 1, 2019
    Publication date: May 13, 2021
    Inventors: Guang-Feng DENG, Cheng-Hung TSAI, Han-Wen LIU, Chih-Chung CHIEN, Chuan-Wen CHEN
  • THERMAL INSULATING CONTAINER WITH A COMBINATION INNER LINER
    Publication number: 20210130074
    Abstract: Disclosed is a thermal insulating container with a combination inner liner, which includes a cup, surrounded with a storage space and forming an open end. The inner edge of the open end has an inner locking part. An inner liner is surrounded with a bearing space and forms an opening end, wherein the inner liner is fitted in the storage space, and the opening end is provided with a screw thread section. There is a connecting part under the screw thread section. An external member is assembled on the connecting part, and there is an outer locking part on the external surface of the external member. The outer locking part is assembled with the inner locking part of the cup body. A cover has an edge which is a circumferential wall extended downwards, and is provided with a ridge section screwed on/off the screw thread section of the inner liner.
    Type: Application
    Filed: June 3, 2020
    Publication date: May 6, 2021
    Inventor: Ching-Wen LIU
  • Metal gate scheme for device and methods of forming
    Patent number: 10998415
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Metal gate stack having TaAlCN layer
    Patent number: 10998194
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • FinFET with sloped surface at interface between isolation structures and manufacturing method thereof
    Patent number: 10998235
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • FinFET structure and method for fabricating the same
    Patent number: 10998425
    Abstract: A device includes a fin structure protruding over a substrate, wherein the fin structure comprises a plurality of portions formed of different materials, a first carbon doped layer formed between two adjacent portions of the plurality of portions, a second carbon doped layer formed underlying a first source/drain region and a third carbon doped layer formed underlying a second source/drain region.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: May 4, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • CURRENT DETECTION DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20210123955
    Abstract: A current detection device including two conductors, a resistor and two detection portions is provided. The resistor is disposed between the two conductors. At least one of the detection portions is a detection terminal including a first terminal portion and a second terminal portion. The first terminal portion includes a first flange and a second flange, the second flange is connected to the second terminal portion, and at least one portion of the second flange is buried into at least one conductor. The first flange is buried into the at least one conductor, a distal end of the first flange does not protrude beyond the second surface, a distance is kept between the distal end of the first flange and the second surface, a gap is defined between the first flange and the second flange, and at least one portion of the gap is filled with a material of the at least one conductor.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 29, 2021
    Applicant: CYNTEC CO., LTD.
    Inventor: PO-WEN LIU
  • TWO-NODE HIGH AVAILABILITY STORAGE SYSTEM
    Publication number: 20210124658
    Abstract: Aspects of the present invention disclose a method for a two-node storage system. The method includes one or more processors creating a plurality of first logic unit groups in a first storage node of a storage system. The method further includes mapping each of the plurality of first logic unit groups to a number of storage slices from different storage devices in the first storage node. The method further creating a plurality of second logic unit groups in a second storage node of the storage system, by mirroring storage slices from a storage device in the first storage node to multiple storage devices in the second storage node. In response to identifying a failure of a first storage device in the first storage node, the method further includes recovering lost data based on data in the second storage node.
    Type: Application
    Filed: October 29, 2019
    Publication date: April 29, 2021
    Inventors: Long Wen Lan, Wen Wu Na, Xiang Wen Liu, Xiao Yu Wang
  • Material for removing contaminants from water
    Patent number: 10987653
    Abstract: A composite comprises a carbonaceous and a metallic nanotube conjugated with a carbonaceous support. The composite may be used to remove contaminants from water.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 27, 2021
    Assignee: AUBURN UNIVERSITY
    Inventors: Dongye Zhao, Wen Liu
  • Integrated Circuit Structure and Method with Solid Phase Diffusion
    Publication number: 20210118997
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20210118807
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of an interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: December 7, 2020
    Publication date: April 22, 2021
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Track bank chargeback sensitivity using disproportional risk level sampling design
    Patent number: 10984422
    Abstract: Examples described herein generally relate to a computer device including a memory, and at least one processor configured to process a transaction. The computer device receives customer transaction information. The computer device evaluates the customer transaction information to determine a risk score for the transaction. The computer device assigns the transaction, based on the risk score, to one of a plurality of stratums including at least a first stratum and a second stratum. The computer device selects a merchant identifier (MID) from at least a first MID associated with the first stratum and a second MID associated with the second stratum based on at least the assigned stratum and a target chargeback rate for at least one of the first MID or the second MID. The computer device transmits the transaction information and the selected MID to an issuing bank.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 20, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Adam Feldman Reinhardt, Yung-Wen Liu, Shoou-Jiun Wang, Jayaram N. M. Nanduri
  • OFF CHIP DRIVER STRUCTURE
    Publication number: 20210111173
    Abstract: An off chip driver structure includes a plurality of pull-up transistors, a plurality of pull-down transistors, a plurality of first regions of a first type, a plurality of second regions of a second type and a plurality of resistor components. The first regions and the second regions are staggered to form an electrostatic discharge (ESD) component. One of the resistor components is coupled to one of the pull-up transistors or one of the pull-down transistors, the resistor components are arranged between the first regions and the second regions.
    Type: Application
    Filed: October 15, 2019
    Publication date: April 15, 2021
    Inventors: Fang-Wen LIU, Tseng-Fu LU
  • Antifuse array and method of forming antifuse using anodic oxidation
    Patent number: 10978461
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: April 13, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company Limited, National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Semiconductor device having modified profile metal gate
    Patent number: 10971594
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Imaging system
    Patent number: 10966797
    Abstract: An imaging system includes an image generating device and two reflecting mirrors. The image generating device projects a light toward a gravity direction. The two reflecting mirrors are disposed with respect to each other and one of the two reflecting mirrors is disposed with respect to the image generating device. The light projected by the image generating device forms a virtual image through the two reflecting mirrors in sequence.
    Type: Grant
    Filed: March 26, 2020
    Date of Patent: April 6, 2021
    Assignee: Qisda Corporation
    Inventors: Tsung-Hsun Wu, Ming-Kuen Lin, Hung-Wen Liu