Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11081475
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: August 3, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Patent number: 11082833
    Abstract: This application relates to the field of communications technologies, and in particular, to a profile download technology. In a profile download method, a primary device obtains an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID; receives the profile download information from the mobile operator server; and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.
    Type: Grant
    Filed: July 30, 2020
    Date of Patent: August 3, 2021
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Feng Li, Wen Liu, Chunlai Feng, Tao Li, Xiaolin Li, Xutao Gao, Wenhua Li
  • Patent number: 11075278
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: July 27, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 11075132
    Abstract: An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second redistribution structure. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die is disposed over the first surface of the first redistribution structure and is electrically connected to the first redistribution structure. The encapsulant encapsulates the die. The conductive structures are disposed on the first surface of the first redistribution structure and penetrates the encapsulant. The conductive structures surround the die. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: July 27, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Shih-Ting Hung, Yi-Jou Lin, Tzu-Jui Fang, Po-Yao Chuang
  • Publication number: 20210226029
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Publication number: 20210223308
    Abstract: The present disclosure provides a dual-sided wafer imaging apparatus and methods thereof. The dual-sided wafer imaging apparatus includes one or more load ports, one or more mechanical arms for transporting a wafer, a wafer transfer stage, a first line scan camera mounted below the wafer transfer stage, a second line scan camera mounted above the wafer transfer stage, a first optical lens mounted on the first line scan camera, a second optical lens mounted on the second line scan camera, and line light sources respectively mounted below and above the wafer transfer stage. The load ports are configured for an automated load operation or unload operation of a wafer pod of an automated transport equipment. The wafer transfer stage includes vacuum suction points in contact with a backside of the wafer, and the wafer transfer stage further includes a drive motor producing a linear reciprocating motion for moving the wafer.
    Type: Application
    Filed: January 22, 2020
    Publication date: July 22, 2021
    Inventors: YING-CHUAN WANG, YI-WEN LIU, SHIH-CHIH LIN, JIH-CHENG HUANG
  • Publication number: 20210221982
    Abstract: An opaque high-impact methyl methacrylate-butadiene-styrene polymer (MBS) for improving impact resistance of polyvinyl chloride (PVC) including the following components by mass: 80-95% of core layer, 4-20% of shell layer and 0.001-0.05% of protective colloid, where the core layer is a butadiene (B) and styrene (S) polymer, the shell layer is one or a copolymer of two or three of S, acrylate and methyl methacrylate (MMA), and the protective colloid includes one or a compound of two or three of polyvinyl alcohol (PVA), gelatin and hydroxypropylmethyl cellulose (HPMC), may solve the problems of low impact resistance in the existing MBS product and difficult coagulation or spraying in the post-treatment process.
    Type: Application
    Filed: December 13, 2019
    Publication date: July 22, 2021
    Applicant: SHANDONG DONGLIN NEW MATERIALS CO., LTD
    Inventors: Xiaoquan ZHANG, Tonggang YI, Yongquan XIA, Honggang ZHAO, Wen LIU, Boxiao ZOU, Duo XU, Xiaomin MA
  • Publication number: 20210206670
    Abstract: The invention relates to composite compositions including a carbonaceous material and a photocatalyst. The invention includes compositions and various methods, including methods for removing one or more contaminants from a substance such as air, soil, and water.
    Type: Application
    Filed: September 25, 2020
    Publication date: July 8, 2021
    Inventors: Dongye ZHAO, Wen LIU, Fan LI, Tianyuan XU, Yangmo ZHU, Jun DUAN, Zongsu WEI
  • Patent number: 11055330
    Abstract: A computer-implemented method for utilizing external knowledge and memory networks in a question-answering system includes receiving, from a search engine of a question-answering system, one or more search results based on a search query associated with a question submitted via a user interface associated with a computing device, analyzing the one or more search results to generate search evidence as a source of external knowledge for generating an answer to the question, the search evidence including one or more titles and one or more corresponding text snippets, encoding the search evidence and the search query to generate vectors stored in a memory network, obtaining a final vector representation based on the encoding, and decoding the final vector representation to obtain the answer to the question.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: July 6, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Peng Wang, Shi Lei Zhang, Wen Liu, Feng Jin, Qin Shi, Yong Qin
  • Patent number: 11056445
    Abstract: Package structures are provided. A package structure includes an adhesive layer and a semiconductor substrate over the adhesive layer. The package structure also includes a connector over the semiconductor substrate. The package structure further includes a first buffer layer surrounding the connector. In addition, the package structure includes an encapsulation layer surrounding the first buffer layer. The first buffer layer is sandwiched between the encapsulation layer and the semiconductor substrate, and a sidewall of the encapsulation layer is in direct contact with a sidewall of the first buffer layer and a sidewall of the adhesive layer. The package structure also includes a redistribution layer over the first buffer layer and the encapsulation layer.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: July 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
  • Publication number: 20210202518
    Abstract: A memory device includes a substrate. A first dielectric layer is disposed over the substrate. A plurality of conductive layers and a plurality of dielectric layers are alternately and horizontally disposed on the substrate. A channel column structure is disposed on the substrate and in the conductive layers and the dielectric layers. A side wall of the channel column structure is in contact with the plurality of conductive layers. A second dielectric layer covers the first dielectric layer. A conductive column structure is in the first and second dielectric layers, adjacent to the channel column structure, and in contact with one of the plurality of conductive layers. The conductive column structure includes a liner insulating layer as a shell layer.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 1, 2021
    Applicant: MACRONIX International Co., Ltd.
    Inventors: YAO-AN CHUNG, Yuan-Chieh Chiu, Ting-Feng Liao, Kuang-Wen Liu, Kuang-Chao Chen
  • Patent number: 11049813
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 29, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 11049490
    Abstract: An audio playback device receives an instruction from a user to select a target voice model from a plurality of voice models and assigns the target voice model to a target character in a text. The audio playback device also transforms the text into a speech, and during the process of transforming the text into the speech, transforms sentences of the target character in the text into the speech of the target character according to the target voice model.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 29, 2021
    Assignee: Institute For Information Industry
    Inventors: Guang-Feng Deng, Cheng-Hung Tsai, Tsun Ku, Zhi-Guo Zhu, Han-Wen Liu
  • Patent number: 11043376
    Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.
    Type: Grant
    Filed: April 14, 2020
    Date of Patent: June 22, 2021
    Assignees: Taiwan Semiconductor Manufacturing Company, Ltd., National Taiwan University
    Inventors: Sheng-Ting Fan, Pin-Shiang Chen, Chee Wee Liu, Chi-Wen Liu
  • Patent number: 11037921
    Abstract: An off chip driver structure includes a plurality of pull-up transistors, a plurality of pull-down transistors, a plurality of first regions of a first type, a plurality of second regions of a second type and a plurality of resistor components. The first regions and the second regions are staggered to form an electrostatic discharge (ESD) component. One of the resistor components is coupled to one of the pull-up transistors or one of the pull-down transistors, the resistor components are arranged between the first regions and the second regions.
    Type: Grant
    Filed: October 15, 2019
    Date of Patent: June 15, 2021
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu
  • Publication number: 20210166972
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: February 9, 2021
    Publication date: June 3, 2021
    Inventors: Che-Liang CHUNG, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Patent number: 11024718
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 11018131
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: July 17, 2018
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Publication number: 20210153368
    Abstract: A handle extension structure includes a connection assembly and an operation assembly. The connection assembly has a first end and a second end opposite to each other. The operation assembly is slidably disposed at the connection assembly. The operation assembly includes an extension element and a grip element. The extension element has a first end portion and a second end portion opposite to each other. The first end portion is slidably disposed between the first end and the second end. The grip element is pivoted to the second end portion. An electronic device casing includes a body, a movable apparatus, and the handle extension structure. The handle extension structure is pivoted to the movable apparatus through the connection assembly.
    Type: Application
    Filed: November 3, 2020
    Publication date: May 20, 2021
    Applicant: PEGATRON CORPORATION
    Inventors: Long-Sing Ye, Yao-Hsien Huang, Yu-Wen Liu
  • Publication number: 20210153371
    Abstract: An electronic device casing includes a body, a movable apparatus, and a handle structure. The body comprises a first stopping surface and a second stopping surface disposed opposite to each other. The movable apparatus is adapted to be detachably assembled in the body. The handle structure is pivotally disposed to the movable apparatus. The handle structure comprises a first arm corresponding to the first stopping surface and a second arm corresponding to the second stopping surface. The movable apparatus is adapted to move between a removed position and an assembled position by rotating the handle structure between an upper pulled position and a lower pressed position.
    Type: Application
    Filed: November 6, 2020
    Publication date: May 20, 2021
    Applicant: PEGATRON CORPORATION
    Inventor: Yu-Wen Liu