Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • METHODS OF FORMING MULTI-CHIP WAFER LEVEL PACKAGES
    Publication number: 20200343220
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • COMPUTATION PLATFORM AGNOSTIC DATA CLASSIFICATION WORKFLOWS
    Publication number: 20200334293
    Abstract: Various embodiments include a classification platform system. A user can define a classification experiment on the classification platform system. For example, the user can define an input data space by selecting at least one of data sources interfaced with the classification platform system and defining a workflow configuration including a directed graph (DG) connecting a plurality of transformation blocks to represent an experiment workflow. The DG can specify how one or more outputs of each of the transformation blocks are fed into one or more other transformation blocks. The DG can be executed by various types of computation platforms. The classification platform system can schedule the experiment workflow to be executed on a distributed computation platform according to the input data space and the workflow configuration.
    Type: Application
    Filed: June 29, 2020
    Publication date: October 22, 2020
    Inventors: Szymon Piechowicz, Barak Reuven Naveh, Annie Hsin-Wen Liu, Ashish Gupta
  • System and method of chemical mechanical polishing
    Patent number: 10800004
    Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Wen Liu, Hao-Yun Cheng, Che-Hao Tu, Kei-Wei Chen
  • Electrostatic-Precipitator Air Cleaner
    Publication number: 20200306766
    Abstract: An electrostatic-precipitator air cleaner includes a base, a shell, a fan, a barrel, a high-voltage discharge module, a distribution module and a precipitation module. The shell is connected to the base. The fan is connected to an upper portion of the shell. The barrel is connected to the shell above the base. The high-voltage discharge module is connected to the base and inserted in the barrel. The distribution module is connected to the high-voltage discharge module. The precipitation module is inserted in the barrel.
    Type: Application
    Filed: January 6, 2020
    Publication date: October 1, 2020
    Inventor: Ching-Wen Liu
  • TOUCH DISPLAY AND METHOD FOR CONTROLLING THE SAME
    Publication number: 20200310566
    Abstract: A touch display and method for controlling the same are provided. The touch display includes a gate driver circuit, a touch sensor and a display panel. The method includes: when the touch sensor detects no touch input signal, the gate driver circuit outputs a plurality of first gate signals to the display panel at a first frequency; and when the touch sensor detects a touch input signal, the gate driver circuit outputs a plurality of second gate signals to the display panel at a second frequency. The second frequency is smaller than the first frequency.
    Type: Application
    Filed: March 24, 2020
    Publication date: October 1, 2020
    Inventors: CHI-CHENG CHEN, GUI-WEN LIU
  • Clamshell electronic device
    Patent number: 10788854
    Abstract: A clamshell electronic device is provided. The clamshell electronic device includes a device body, a cover, an auxiliary display unit and an orientation adjustment mechanism. The cover pivots on the device body, and the cover includes a cover notch. The auxiliary display unit is disposed on the device body, wherein the auxiliary display unit is adapted to be rotated between a first unit orientation and a second unit orientation. The orientation adjustment mechanism is connected to the cover and the auxiliary display unit, wherein when the cover is in a first cover orientation relative to the device body, the cover covers the device body, and the auxiliary display unit is in the first unit orientation and corresponds to the cover notch. The user can obtain information such as time, weather or messages directly via the auxiliary display unit in the the cover notch.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: September 29, 2020
    Assignee: WISTRON CORP.
    Inventors: Chen Yi Liang, Chen-Wen Liu, Ming-Ju Hsieh, Tzu Yuan Tseng, Chun Yi Lu, Ko-Chen Chang
  • Specialist keywords recommendations in semantic space
    Patent number: 10789298
    Abstract: Techniques are provided for generating recommended query terms that are specialized to a topic of desired information based on a query associated with a user. In one example, a computer-implemented method comprising selecting, by a system operatively coupled to a processor, a coarse cluster of corpus terms having a defined relatedness to a query associated with a user from a plurality of coarse clusters of corpus terms; and determining, by the system, a plurality of candidate terms from search results associated with the query. The computer-implemented method can also comprise determining, by the system, at least one recommended query term based on refined clusters of the coarse cluster, the candidate terms, and the query; and displaying, by the system, the at least one recommended query term on a display device associated with the query.
    Type: Grant
    Filed: November 16, 2016
    Date of Patent: September 29, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Feng Jin, Wen Liu, Yong Qin, Qin Shi, Peng Wang, Shi Lei Zhang
  • Semiconductor arrangement and formation thereof
    Patent number: 10790197
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Grant
    Filed: December 16, 2019
    Date of Patent: September 29, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: I-Wen Wu, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Fin Spacer Protected Source and Drain Regions in FinFETs
    Publication number: 20200303258
    Abstract: A method includes forming Shallow Trench Isolation (STI) regions in a semiconductor substrate and a semiconductor strip between the STI regions. The method also include replacing a top portion of the semiconductor strip with a first semiconductor layer and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer has a first germanium percentage higher than a second germanium percentage of the second semiconductor layer. The method also includes recessing the STI regions to form semiconductor fins, forming a gate stack over a middle portion of the semiconductor fin, and forming gate spacers on sidewalls of the gate stack. The method further includes forming fin spacers on sidewalls of an end portion of the semiconductor fin, recessing the end portion of the semiconductor fin, and growing an epitaxial region over the end portion of the semiconductor fin.
    Type: Application
    Filed: June 8, 2020
    Publication date: September 24, 2020
    Inventors: Kuo-Cheng Chiang, Ting-Hung Hsu, Chao-Hsiung Wang, Chi-Wen Liu
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20200294973
    Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zhi-Qiang WU, Chun-Fu CHENG, Chung-Cheng WU, Yi-Han WANG, Chia-Wen LIU
  • Semiconductor Device Package and Method
    Publication number: 20200294870
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Application
    Filed: June 1, 2020
    Publication date: September 17, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Wrap Around Silicide for FinFETs
    Publication number: 20200287041
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • CLAMSHELL ELECTRONIC DEVICE
    Publication number: 20200285273
    Abstract: A clamshell electronic device is provided. The clamshell electronic device includes a device body, a cover, an auxiliary display unit and an orientation adjustment mechanism. The cover pivots on the device body, and the cover includes a cover notch. The auxiliary display unit is disposed on the device body, wherein the auxiliary display unit is adapted to be rotated between a first unit orientation and a second unit orientation. The orientation adjustment mechanism is connected to the cover and the auxiliary display unit, wherein when the cover is in a first cover orientation relative to the device body, the cover covers the device body, and the auxiliary display unit is in the first unit orientation and corresponds to the cover notch.
    Type: Application
    Filed: July 24, 2019
    Publication date: September 10, 2020
    Inventors: Chen Yi LIANG, Che-Wen LIU, Ming-Ju HSIEH, Tzu Yuan TSENG, Chun Yi LU, Ko-Chen CHANG
  • FINFET DEVICES AND METHODS OF FORMING
    Publication number: 20200279781
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu
  • Multi-chip wafer level packages and methods of forming the same
    Patent number: 10763239
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Profile download method and device
    Patent number: 10764745
    Abstract: This application relates to the field of communications technologies, and in particular, to a profile download technology. In a profile download method, a primary device obtains an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID; receives the profile download information from the mobile operator server; and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: September 1, 2020
    Assignee: HUAWEI TECHNOLOGIES CO., LTD.
    Inventors: Feng Li, Wen Liu, Chunlai Feng, Tao Li, Xiaolin Li, Xutao Gao, Wenhua Li
  • Stacked gate-all-around FinFET and method forming the same
    Patent number: 10763368
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Touch sensing system and data transmission method of a touch panel
    Patent number: 10754479
    Abstract: A data transmission method applied to a touch panel includes: determining an overlapped quantity of at least one first touch electrode pad and at least one second touch electrode pad that are electrically coupled to each other; determining a transmission bit number according to the overlapped quantity; and making the at least one first touch electrode pad transmit at least one data signal to the at least one second touch electrode pad according to the transmission bit number and a transmission frequency, where the at least one first touch electrode pad is configured on a first electronic apparatus, and the at least one second touch electrode pad is configured on a second electronic apparatus.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: August 25, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Shan-Kang Chen, Gui-Wen Liu
  • Structure and formation method for chip package
    Patent number: 10748882
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: September 10, 2018
    Date of Patent: August 18, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Field-effect transistors having contacts to 2D material active region
    Patent number: 10741646
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Grant
    Filed: May 6, 2019
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu