Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEMS AND METHODS FOR AUTHENTICATING AN ELECTRONIC TRANSACTION
    Publication number: 20200402054
    Abstract: Devices and methods for securing electronic transactions in a computing network are configured to receive a transaction, access transaction contextual data for the transaction, and apply one or more authentication decision rules to the transaction contextual data to determine initial authentication assessment information for the transaction. Further, aspects are configured to convert the initial authentication assessment information into a condensed authentication assessment indicator having an assessment value selected from a plurality of assessment values based on an assessment value definition, and transmit the condensed authentication assessment indicator. Also, aspects receive a transaction authentication decision based in part on the condensed authentication assessment indicator, and process or deny processing of the transaction based on the transaction authentication decision.
    Type: Application
    Filed: October 14, 2019
    Publication date: December 24, 2020
    Inventors: Murali Krishna MANJUNATH, Yuting JIA, Adam REINHARDT, Yung-Wen LIU, Anand Ravindra OKA, Jayaram N.M. NANDURI
  • METHOD FOR PURIFYING 2-[[2-[[[3-(4-CHLOROPHENYL)-8-METHYL-8-AZABICYCLO-[3.2.1]-OCT-2-YL]METHYL](2-MERCAPTOETHYL)AMINO]ETHYL]AMINO]ETHANETHIOL-[1R-(EXO-EXO)]TRIHYDROCHLORIDE
    Publication number: 20200392134
    Abstract: A method for purifying 2-[[2-[[[3-(4-Chlorophenyl)-8-methyl-8-azabicyclo[3.2.1]-oct-2-yl]methyl](2-mercaptoethyl)amino]ethyl]amino]ethanethiol-[1R-(exo-exo)]-hydrochloride is revealed. After medium pressure liquid chromatography and subsequent acid treatment, 2-[[2-[[[3-(4-Chlorophenyl)-8-methyl-8-azabicyclo[3.2.1]-oct-2-yl]methyl](2-mercaptoethyl)amino]ethyl]amino]ethanethiol-[1R-(exo-exo)]-hydrochloride with high purity is obtained. The method for purifying can solve the problem that the product purity is not up to the standard for radiopharmaceuticals.
    Type: Application
    Filed: May 12, 2020
    Publication date: December 17, 2020
    Inventors: SHOW-WEN LIU, CHENG-FANG HSU, WEI-HSI CHEN, YU CHANG
  • MULTI-CHIP WAFER LEVEL PACKAGES
    Publication number: 20200395335
    Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.
    Type: Application
    Filed: August 30, 2020
    Publication date: December 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Han-Hsiang Huang, Hsien-Wen Liu, Shin-Puu Jeng, Hsiao-Wen Lee
  • Semiconductor package with redistribution structure and pre-made substrate on opposing sides for dual-side metal routing
    Patent number: 10867924
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Devices including gate spacer with gap or void and methods of forming the same
    Patent number: 10868150
    Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Ching-Wei Tsai, Chi-Wen Liu, Ying-Keung Leung
  • Semiconductor structure and method of fabricating wiring structure
    Patent number: 10867909
    Abstract: The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: December 15, 2020
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Meng-Han Tsai, Yi-Chen Wang, Kuan-Chih Chen, Kuang-Wen Liu
  • SEMICONDUCTOR STRUCTURE WITH MASK STRUCTURE
    Publication number: 20200388498
    Abstract: Semiconductor structures are provided. The semiconductor structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor structure further includes a sealing layer comprising an inner sidewall and an outermost sidewall. In addition, the inner sidewall is in direct contact with the metal gate structure and the outermost sidewall is away from the metal gate structure. The semiconductor structure further includes a mask structure formed over the metal gate structure. In addition, the mask structure has a straight sidewall over the metal gate structure and a sloped sidewall extending from the inner sidewall of the sealing layer and passing over the outmost sidewall of the sealing layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: December 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
  • Interconnection structure, fabricating method thereof, and semiconductor device using the same
    Patent number: 10861791
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Integrated circuit structure and method with solid phase diffusion
    Patent number: 10861937
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.
    Type: Grant
    Filed: December 13, 2018
    Date of Patent: December 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Wafer level package (WLP) and method for forming the same
    Patent number: 10861801
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: November 26, 2019
    Date of Patent: December 8, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Structure and Formation Method for Chip Package
    Publication number: 20200381407
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Application
    Filed: August 17, 2020
    Publication date: December 3, 2020
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING WIRING STRUCTURE
    Publication number: 20200381356
    Abstract: The semiconductor structure includes a semiconductor device, a first metallization layer on the semiconductor device, a second metallization layer on the first metallization layer, and a third dielectric layer between the first metallization layer and the second metallization layer. The first metallization layer includes a first dielectric layer and a first metal layer disposed in the first dielectric layer, wherein the first metal layer has a first thickness, and the first metal layer comprises copper. The third dielectric layer has a second thickness, and a ratio of the second thickness of the third dielectric layer to the first thickness of the first metal layer is ranged from about 3 to about 20.
    Type: Application
    Filed: June 20, 2019
    Publication date: December 3, 2020
    Inventors: Meng-Han TSAI, Yi-Chen WANG, Kuan-Chih CHEN, Kuang-Wen LIU
  • Earphone device
    Patent number: 10856066
    Abstract: The invention discloses an earphone device comprising a first case, a first speaker unit, a first recording unit, and a second recording unit. The first speaker unit, disposed inside the first case, emits a first testing sound signal according to a test command. The first recording unit, disposed inside the first case, records a first environment sound signal according to a record command or a noise cancelling command. The second recording unit, disposed inside the first case, records a first feedback sound signal, related to the first testing sound signal, according to the test command.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: December 1, 2020
    Assignee: XROUND INC.
    Inventors: Peng Lee, Yi-Wen Liu
  • One-dimensional nanostructure growth on graphene and devices thereof
    Patent number: 10854724
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Grant
    Filed: November 19, 2018
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Che-Wei Yang, Chi-Wen Liu, Hao-Hsiung Lin, Ling-Yen Yeh
  • WAFER LEVEL MOLD CHASE
    Publication number: 20200365421
    Abstract: A mold chase is provided, including a lower mold support and an upper mold support which are configured to be pressed together to form a mold cavity therebetween for receiving a wafer level substrate. The mold chase also includes multiple gates and at least one vent disposed along the periphery of the mold cavity. The gates are configured to allow a mold material to be injected into the mold cavity, and the vents are configured to release gas from the mold cavity. The distance between one of the gates and the closest vent is less than the diameter of the mold cavity.
    Type: Application
    Filed: May 16, 2019
    Publication date: November 19, 2020
    Inventors: Hsien-Wen LIU, Po-Hao TSAI, Yi-Wen WU, Shin-Puu JENG
  • FinFET structure with different fin heights and method for forming the same
    Patent number: 10840126
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: November 17, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Strained Nanowire CMOS Device and Method of Forming
    Publication number: 20200357885
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • IMAGING SYSTEM
    Publication number: 20200345450
    Abstract: An imaging system includes an image generating device and two reflecting mirrors. The image generating device projects a light toward a gravity direction. The two reflecting mirrors are disposed with respect to each other and one of the two reflecting mirrors is disposed with respect to the image generating device. The light projected by the image generating device forms a virtual image through the two reflecting mirrors in sequence.
    Type: Application
    Filed: March 26, 2020
    Publication date: November 5, 2020
    Inventors: Tsung-Hsun Wu, Ming-Kuen Lin, Hung-Wen Liu
  • Self-aligned contact and manufacturing method thereof
    Patent number: 10825907
    Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo
  • FINFET WITH SLOPED SURFACE AT INTERFACE BETWEEN ISOLATION STRUCTURES AND MANUFACTURING METHOD THEREOF
    Publication number: 20200343141
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: July 14, 2020
    Publication date: October 29, 2020
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu