Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.

Abstract: Systems and methods of the present disclosure generally relate to a partitioned stator. The stator includes a plurality of partitioned iron cores that are identical in shape and connected to each other. Windings are wrapped around the partitioned iron cores. Each partitioned iron core includes a yoke and a tooth. End-face enlargements are symmetrically arranged on two end-faces of the yoke. The yoke is of an arc-shaped structure, and the end-face enlargements extend in a radial direction of the arc-shaped structure.

Abstract: A method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked in a first direction over a substrate, the first semiconductor layers being thicker than the second semiconductor layers. The method also includes patterning the stacked structure into a first fin structure and a second fin structure extending along a second direction substantially perpendicular to the first direction. The method further includes removing the first semiconductor layers of the first fin structure to form a plurality of nanowires. Each of the nanowires has a first height, there is a distance between two adjacent nanowires along the vertical direction, and the distance is greater than the first height. The method includes forming a first gate structure between the second semiconductor layers of the first fin structure.

Abstract: A composite comprises a carbonaceous and a metallic nanotube conjugated with a carbonaceous support. The composite may be used to remove contaminants from water.

Abstract: A call record synchronization method includes detecting, by a first terminal, an input operation for requesting to display a call record. The method further includes, after the first terminal detects the input operation, displaying, by the first terminal, a merged call record, where the merged call record is a call record obtained after merging of a call record of the first terminal and a call record of a second terminal. The merged call record includes a device identifier of the first terminal and/or a device identifier of the second terminal.

Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.

Abstract: Embodiments of the present disclosure relate to object detection in an image. In an embodiment, a computer-implemented method is disclosed. According to the method, image data representing a scene is obtained and sound distribution information related to the scene is obtained. A detection strategy to be applied in object detection is determined based on the sound distribution information. The object detection is performed on the image data by applying the detection strategy. In other embodiments, a system and a computer program product are disclosed.

Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: The present invention provides for compounds of Formula I-I and embodiments and salts thereof for the treatment of diseases (e.g., neurodegenerative diseases). R1, R2, R3, X1, X2, A and Cy variable in Formula I-I all have the meaning as defined herein.

Abstract: A transistor based on topological insulators is provided. In an embodiment a topological insulator is used to form both the channel as well as the source/drain regions, wherein the channel has a first thickness such that the topological insulator material has properties of a semiconductor material and the source/drain regions have a second thickness such that the topological insulator has properties of a conductive material.

Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.

Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.

Abstract: A touch display panel includes a first sensing matrix and a second sensing matrix. The first sensing matrix includes a plurality of grid units and a first switch unit. The grid units are arranged in matrix, wherein each grid unit includes at least one first electrode. The first switch unit includes a plurality of switches, and the switches are disposed between adjacent grid units. Wherein, the control end of the switches is configured to receive a first controlling signal, and one end of each of the switches is configured to output a sensing signal. The second sensing matrix includes at least one second electrode, and is configured to receive a common signal. The second sensing matrix includes a plurality of opening units, and each opening unit overlaps with the open area of each pixel circuit in a vertical projection direction of the first substrate.

Abstract: A mold chase is provided, including a lower mold support and an upper mold support which are configured to be pressed together to form a mold cavity therebetween for receiving a wafer level substrate. The mold chase also includes multiple gates and at least one vent disposed along the periphery of the mold cavity. The gates are configured to allow a mold material to be injected into the mold cavity, and the vents are configured to release gas from the mold cavity. The distance between one of the gates and the closest vent is less than the diameter of the mold cavity.

Abstract: An IC package having a metal die for ESD protection includes: a printed circuit board having power connections and ground connections; a function die; and a metal die adhered unto the function die and electrically insulated from the function die, wherein the metal die comprises a metal layer and a dummy die underlying the metal layer, and the metal layer is electrically coupled to one or more of the power connections and ground connections of the printed circuit board to provide package level electrostatic discharge (ESD) protection; and an encapsulant covering the metal die, the function die and a surface of the printed circuit board supporting the metal die and function die.

Abstract: An engagement structure for a tool contains: a drive member which includes an accommodation orifice, a hexagonal tooth portion, and six planes. A respective one of the six planes is arranged on a center of a respective one of six peripheral sides of the hexagonal tooth portion, and the two beveled rims extends from the two sides of the respective one plane and are connected with a first adjacent beveled rim of a first adjacent plane and a second adjacent beveled rim of a second adjacent plane. A ratio of lengths of the respective one plane, the first adjacent beveled rim and the second adjacent beveled rim is 2:1:2, and an angle between the respective one plane and each of the first adjacent beveled rims and the second adjacent beveled rim is 2 degrees.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: Disclosed is a flue gas purification tower, comprising a tower body, at least one gas inlet (1) disposed at the bottom of the tower body, at least one gas outlet (2) disposed at the top of the tower body, at least one active coke layer (3) located inside the tower body, and a baffle plate (4) arranged in a place where the flow direction of the flue gas from the gas inlet changes. The baffle plate (4) is a straight plate, an arc plate, a straight-and-arc plate or a straight-arc-straight plate, wherein the straight-and-arc plate comprises a straight segment and an arc segment connected with each other; and the straight-arc-straight plate comprises a straight segment in the vertical direction, a straight segment in the horizontal direction, and an arc segment connected between the two straight segments.

Abstract: An IC package having a metal die for ESD protection includes: a printed circuit board having power connections and ground connections; a function die; and a metal die adhered unto the function die and electrically insulated from the function die, wherein the metal die comprises a metal layer and a dummy die underlying the metal layer, and the metal layer is electrically coupled to one or more of the power connections and ground connections of the printed circuit board to provide package level electrostatic discharge (ESD) protection; and an encapsulant covering the metal die, the function die and a surface of the printed circuit board supporting the metal die and function die.