Abstract: Devices and structures that include a gate spacer having a gap or void are described along with methods of forming such devices and structures. In accordance with some embodiments, a structure includes a substrate, a gate stack over the substrate, a contact over the substrate, and a spacer disposed laterally between the gate stack and the contact. The spacer includes a first dielectric sidewall portion and a second dielectric sidewall portion. A void is disposed between the first dielectric sidewall portion and the second dielectric sidewall portion.

Abstract: The present disclosure relates to a field of construction engineering, and in particular to a reinforcing structure of a concrete overhead layer before a building expires. The reinforcing structure of the concrete overhead layer includes supporting structures, connecting structures, and metal members; wherein the reinforcing structure is configured to reinforce a concrete floor slab and/or a concrete beam; through holes are disposed on the concrete floor slab; each of the supporting structures passes through each of the through holes and the supporting structures are configured to support the concrete floor slab and/or the concrete beam; and each of the connecting structures is configured to fix each of the supporting structures on each of the metal members; each of the metal members is disposed on each of the through holes.

Abstract: A semiconductor structure includes a substrate, at least one first conductive structure, at least one second conductive structure, at least one first memory structure, and at least one second memory structure. The substrate has an array region and a dummy region. The first conductive structure is disposed on the array region. The second conductive structure is disposed on the dummy region. The first memory structure is disposed on the first conductive structure. The first memory structure includes a first channel layer, and the first channel layer is in contact with the first conductive structure. The second memory structure is disposed on the second conductive structure. The second memory structure includes a second channel layer, and the second channel layer is isolated from the second conductive structure.

Abstract: The present invention relates to a reinforcing structure of unexpired concrete building floors used for reinforcing a concrete column, a concrete beam and a concrete floor slab. The structure has: at least one external column each of the at least one external column wrapping around the concrete column; at least one framework each wrapping around the concrete beam; a plurality of brackets fixedly mounted to the lower surface of the concrete floor slab, and a base plate disposed at the bottom of the concrete column, wherein the bottom of each of the at least one external column is fixed to the base plate, the top of each of the at least one external column is fixed to a corresponding one of the at least one framework, and the corresponding framework is fixed to the plurality of brackets along a length direction of the concrete beam.

Abstract: A system is described herein for managing digital transactions over a network with incomplete information. The system includes a data collection component and a transaction control component that may employ a prospective control model that is trained with fully matured data as well as partially matured data regarding past digital transactions. The transaction control component is configured to estimate an inauthentic rate of inauthentic digital transactions being wrongly approved for a current time period. A set of future reference values may be determined based on the estimated inauthentic rate. The set of future reference values relate to a predicted future decision made for the digital transaction. A set of current values may be determined based on the set of future reference values. Based on the set of current values, the transaction control component may determine whether the digital transaction should be rejected as inauthentic or approved as authentic.

Abstract: Techniques are described that facilitate automatically distinguishing between different expressions of a same or similar emotion. In one embodiment, a computer-implemented is provided that comprises partitioning, by a device operatively coupled to a processor, a data set comprising facial expression data into different clusters of the facial expression data based on one or more distinguishing features respectively associated with the different clusters, wherein the facial expression data reflects facial expressions respectively expressed by people. The computer-implemented method can further comprise performing, by the device, a multi-task learning process to determine a final number of the different clusters for the data set using a multi-task learning process that is dependent on an output of an emotion classification model that classifies emotion types respectively associated with the facial expressions.

Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.

Abstract: An oral irrigator contains: a body, a water tank and a detachable jet tip which are both in connection with the body, a power device and a control device Which are both accommodated in the body. The power device is configured to deliver water from the water tank to the detachable jet tip. The power device includes a first outlet defined thereon and configured to discharge the water, a delivery tube connecting with the first outlet, and a first seal element configured to stop water flowing into the body from the power device so that the water discharges out of the first outlet.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, a heat dissipation baseplate, and a thermal interface layer. The heat dissipation insulating substrate has a first surface and a second surface which are opposite to each other, and the power devices are coupled to the first surface of the heat dissipation insulating substrate. The heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate, wherein at least one of a surface of the heat dissipation baseplate and the second surface of the heat dissipation insulating substrate has at least one plateau, and the plateau is at least disposed within a projected area of the plurality of power devices. The thermal interface layer is disposed between the second surface of the heat dissipation insulating substrate and the surface of the heat dissipation baseplate.

Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.

Abstract: An assembly of a blade assembly bracket and a blade of a ceiling fan includes a blade assembly bracket, an adaptor, and a fan blade. The adaptor is pivoted to the blade assembly bracket, and the fan blade is pivoted to the adaptor. When the adaptor is pivoted relative to the blade assembly bracket, the adaptor can drive the rotatable holder simultaneously to switch a position of the fan blade between an initial position and a rotational position, so as to change an inclination angle of the fan blade, and make the fan blade unfold outwardly. When the operation of the ceil fan is stopped, the adaptor is operated reversely to make the fan blade fold from the outwardly-unfolded state.

Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.

Abstract: A package structure for power devices includes a heat dissipation insulating substrate, a plurality of power devices, at least one conductive clip, and a heat dissipation baseplate. The heat dissipation insulating substrate has a first surface and a second surface opposite thereto, and the power devices form a bridge circuit topology and are disposed on the first surface, wherein active regions of at least one of the power devices are flip-chip bonded to the first surface. The conductive clip is configured to electrically connect at least one of the power devices to the first surface, and the heat dissipation baseplate is disposed at the second surface of the heat dissipation insulating substrate.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: The present disclosure discloses a circuit structure. The circuit structure comprises: a redundant memory device for simulating a read operation of the memory cell in response to the driving of the test word line voltage; a decision device connected to the internal node of the redundant memory device for determining whether the test word line voltage causes the internal node of the redundant memory device to reverse during the read operation in response to the read operation. In response to the reversal, the redundant memory device simulates the read operation with the adjusted test word line voltage until the determination device determines that the internal node does not reverse during the read operation. The circuit structure also comprises: a statistics device for counting and outputting the number of reversals, which is used to characterize the critical word line voltage in conjunction with each adjustment of the test word line voltage.

Abstract: A system controls a flow of a chemical mechanical polish (CMP) slurry into a chamber to form a slurry reservoir within the chamber. Once the slurry reservoir has been formed within the chamber, the system moves a polishing head to position and force a surface of a wafer that is attached to the polishing head into contact with a polishing pad attached to a platen within the chamber. A wafer/pad interface is formed at the surface of the wafer forced into contact with the polishing pad and the wafer/pad interface is disposed below an upper surface of the slurry reservoir. During CMP processing, the system controls one or more of a level, a force, and a rotation of the platen, a position, a force and a rotation of the polishing head to conduct the CMP processing of the surface of the wafer at the wafer/pad interface.

Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

Abstract: A fluorescence image registration method includes obtaining at least one fluorescence image of a biochip. An interior local area. Sums of pixel values in the interior local area along a first direction and a second direction are obtained. A plurality of first template lines is selected to find a minimum total value of the sums of pixel values corresponding to the first template lines. Pixel-level correction is performed on a local area of the track line to obtain a pixel-level track cross. Other track crosses on the biochip is obtained, and the pixel-level correction is performed on the other track crosses. The position of the pixel-level track line is corrected by a center-of-gravity method to obtain the subpixel-level position of the track line. The subpixel-level positions of all sites uniformly distributed on the biochip is obtained.

Abstract: This application relates to the field of communications technologies, and in particular, to a profile download technology. In a profile download method, a primary device obtains an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID; receives the profile download information from the mobile operator server; and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.

Abstract: An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.