Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • DIODE STRUCTURE AND ELECTROSTATIC DISCHARGE PROTECTION DEVICE INCLUDING THE SAME
    Publication number: 20190198492
    Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.
    Type: Application
    Filed: April 19, 2018
    Publication date: June 27, 2019
    Inventors: FANG-WEN LIU, TSENG-FU LU
  • DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
    Publication number: 20190196726
    Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive an inputting data and a temperature signal; a first error-correction code (ECC1) circuit configured to generate a first encoded data from the inputting data; and a second error-correction code (ECC2) circuit configured to generate a second encoded data from the inputting data.
    Type: Application
    Filed: March 12, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, Hsien-Wen Liu
  • HYBRID MEMORY SYSTEM AND METHOD OF OPERATING THE SAME
    Publication number: 20190196733
    Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.
    Type: Application
    Filed: February 20, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • DYNAMIC RANDOM ACCESS MEMORY AND METHOD OF OPERATING THE SAME
    Publication number: 20190196902
    Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive a reading address and a defect information of the reading address; an access circuit configured to generate a reading data from the memory array according to the reading address from the control circuit; and a modifying circuit connected to the access circuit and the control circuit, wherein the modifying circuit is configured to modify a part of the reading data according to the defect information.
    Type: Application
    Filed: February 26, 2018
    Publication date: June 27, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • DRAM and method for determining binary logic using a test voltage level
    Patent number: 10332580
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • DRAM and method for operating the same
    Patent number: 10332579
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: June 25, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Moisture detection and ingression monitoring systems and methods of manufacture
    Patent number: 10324056
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 18, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy
  • FinFET device and fabricating method thereof
    Patent number: 10326006
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: June 18, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng
  • SELF-HEAT PRESERVATION BUILDING STRUCTURE
    Publication number: 20190177967
    Abstract: The present utility model relates to a building structure, and in particular to a self-heat preservation building structure applied to extremely severe cold regions.
    Type: Application
    Filed: May 15, 2018
    Publication date: June 13, 2019
    Applicant: FENG HE YING ZAO GROUP CO., LTD.
    Inventors: Baoru JIE, Jiangang JIE, Hongyang XIE, Zhihui YAO, Shuangxi ZHOU, Sheng QIAN, Yuchun CHEN, Wujin TAO, Wen LIU, Xin HE, Luolong ZHAN
  • DRAM AND METHOD OF OPERATING THE SAME
    Publication number: 20190171572
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Application
    Filed: January 2, 2018
    Publication date: June 6, 2019
    Inventors: CHUNG-HSUN LEE, HSIEN-WEN LIU
  • Moisture detection and ingression monitoring systems and methods of manufacture
    Patent number: 10309919
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: June 4, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy
  • DRAM AND METHOD FOR OPERATING THE SAME
    Publication number: 20190164589
    Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.
    Type: Application
    Filed: February 20, 2018
    Publication date: May 30, 2019
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Handle structure
    Patent number: 10303222
    Abstract: A handle structure including a base portion, a stop portion and a grip portion is provided. The grip portion is connected between the base portion and the stop portion. The handle structure has a cavity therein, the cavity has a bottom surface, and the bottom surface of the cavity is inclined to an axial direction of the grip portion.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: May 28, 2019
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Chun-Chi Wang, Li-Fang Chen, Yi-Wen Liu, Chen-Hsien Cheng
  • Memory device and operating method thereof
    Patent number: 10297304
    Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.
    Type: Grant
    Filed: November 12, 2017
    Date of Patent: May 21, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Interconnection structure, fabricating method thereof, and semiconductor device using the same
    Patent number: 10297548
    Abstract: A semiconductor device includes a semiconductor substrate, an epitaxy structure present in the semiconductor substrate, and a silicide present on a textured surface of the epitaxy structure. A plurality of sputter ions are present between the silicide and the epitaxy structure. Since the surface of the epitaxy structure is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: May 21, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • FETs and Methods for Forming the Same
    Publication number: 20190148555
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • MEMORY DEVICE AND OPERATING METHOD THEREOF
    Publication number: 20190147936
    Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.
    Type: Application
    Filed: November 12, 2017
    Publication date: May 16, 2019
    Inventors: Chung-Hsun LEE, Hsien-Wen LIU
  • FINFET DEVICES AND METHODS OF FORMING
    Publication number: 20190148244
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • GATE DRIVER AND TOUCH DISPLAY APPARATUS THEREOF
    Publication number: 20190146618
    Abstract: A gate driver and a touch display apparatus thereof are provided. The gate driver includes a plurality of shift registers and at least one loop circuit. The shift registers provide multiple gate signals to a touch display module. The loop circuit is coupled in series with the shift registers and receives at least one touch switching signal to set a loop time of the loop circuit. The touch display module performs at least one touch scan during the loop time.
    Type: Application
    Filed: April 1, 2018
    Publication date: May 16, 2019
    Applicant: Au Optronics Corporation
    Inventors: Chi-Cheng Chen, Gui-Wen Liu
  • FinFET Device and Fabricating Method Thereof
    Publication number: 20190148523
    Abstract: A FinFET device includes a substrate, a fin formed on the substrate, and a gate electrode crossing the fin. The gate electrode includes a head portion and a tail portion, and the tail portion is connected to the head portion and extended toward the substrate. The width of the head portion is greater than that of the tail portion.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Yen-Ming Peng, Chi-Wen Liu, Hsin-Chieh Huang, Yi-Ju Hsu, Horng-Huei Tseng