Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200098923
    Abstract: A multi-gate semiconductor device having a fin element, a gate structure over the fin element, an epitaxial source/drain feature adjacent the fin element; a dielectric spacer interposing the gate structure and the epitaxial source/drain feature.
    Type: Application
    Filed: November 26, 2019
    Publication date: March 26, 2020
    Inventors: Huan-Sheng WEI, Hung-Li CHIANG, Chia-Wen LIU, Yi-Ming SHEU, Zhiqiang WU, Chung-Cheng WU, Ying-Keung LEUNG
  • Publication number: 20200093732
    Abstract: The present invention provides a facial mask composition, comprising by weight percentage, the following ingredients: (a) 0.01% to 30% of emollient oil; (b) 0.01% to 20% of moisturizer; (c) 0.01% to 10% of thickening polymer; (d) 0.01% to 10% of skin conditioner; and (e) 10% to 90% of deionized water; wherein, the skin conditioner comprises, by weight parts: Radix Astragali 20, Aloe vera 30, Radix Angelicae Dahuricae 20 and Poria cocos 30.
    Type: Application
    Filed: September 21, 2018
    Publication date: March 26, 2020
    Inventor: Wen Liu
  • Patent number: 10597436
    Abstract: The presently described compounds relate to the treatment of diabetes and/or hyperglycemia. More particularly, the described compounds relate to acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: March 24, 2020
    Assignee: Eli Lilly and Company
    Inventors: Wen Liu, Adam Robert Mezo, Francisco Alcides Valenzuela
  • Publication number: 20200089371
    Abstract: A touch display panel includes a first sensing matrix and a second sensing matrix. The first sensing matrix includes a plurality of grid units and a first switch unit. The grid units are arranged in matrix, wherein each grid unit includes at least one first electrode. The first switch unit includes a plurality of switches, and the switches are disposed between adjacent grid units. Wherein, the control end of the switches is configured to receive a first controlling signal, and one end of each of the switches is configured to output a sensing signal. The second sensing matrix includes at least one second electrode, and is configured to receive a common signal. The second sensing matrix includes a plurality of opening units, and each opening unit overlaps with the open area of each pixel circuit in a vertical projection direction of the first substrate.
    Type: Application
    Filed: August 12, 2019
    Publication date: March 19, 2020
    Inventors: Chia-Chi LEE, Chi-Cheng CHEN, Jing-Siang SYU, Shu-Wen TZENG, Gui-Wen LIU, Zeng-De CHEN, Wen-Rei GUO
  • Publication number: 20200090938
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary gate stack includes a gate dielectric layer disposed over the substrate, a multi-function layer disposed over the gate dielectric layer, and a work function layer disposed over the multi-function layer. The multi-function layer includes a first metal nitride sub-layer having a first nitrogen (N) concentration and a second metal nitride material with a second metal nitride sub-layer having a second N concentration. The second metal nitride sub-layer is disposed over the first metal nitride-sub layer and the first N concentration is greater than the second N concentration. In some implementations, the second N concentration is from about 2% to about 5% and the first N concentration is from about 5% to about 15%.
    Type: Application
    Filed: November 15, 2019
    Publication date: March 19, 2020
    Inventors: SHIU-KO JANGJIAN, TING-CHUN WANG, CHI-CHERNG JENG, CHI-WEN LIU
  • Patent number: 10590159
    Abstract: Provided in the present invention are a class of Lincomycin biosynthetic intermediates and a preparation method and use thereof. Specifically provided are Lincomycin biosynthetic intermediates obtained from the genetic modification of a Lincomycin producing bacterium, and a method for the production thereof through fermentation and purification through separation.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: March 17, 2020
    Assignees: Shanghai Institute of Organic Chemistry, Chinese Academy of Sciences, Huzhou Center of Bio-Synthetic Innovation, Shanghai Institute of Organic Chemistry, Chinese Academy of Sciences
    Inventors: Wen Liu, Min Wang, Dongxiao Xu, Qunfei Zhao, Qinglin Zhang
  • Publication number: 20200083091
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 12, 2020
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Publication number: 20200075742
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Application
    Filed: October 24, 2019
    Publication date: March 5, 2020
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • Patent number: 10579186
    Abstract: A method and a detection circuit for selecting a touch detection time are provided. The method for selecting a touch detection time includes the following steps: detecting a noise signal of a touch panel in a first display frame period; determining whether signal strength of the noise signal in a first time segment in the first display frame period is greater than a first noise threshold; and when the signal strength of the noise signal in the first time segment in the first display frame period is less than the first noise threshold, performing touch control in a second time segment in a second display frame period corresponding to the first time segment.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: March 3, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Szu-Che Yeh, Chi-Cheng Chen, Feng-Ming Hsu, Gui-Wen Liu
  • Patent number: 10580765
    Abstract: A semiconductor structure includes a silicon control rectifier (SCR) region and a NPN region adjacent to the SCR region. The silicon control rectifier (SCR) region includes a first p-well region, a first n-well region surrounded by the first p-well region and a first P+ region in the first p-well region and spaced apart from the first n-well region. The NPN region includes a second p-well region, a first N+ region, a second N+ region and a second P+ region. The first N+ region is coupled to the second p-well region and an electrostatic discharge source. The second N+ region is coupled to the second p-well region and spaced apart from the first N+ region. The second P+ region is disposed in the second p-well region and equipotentially connected to the first P+ region in the first p-well region.
    Type: Grant
    Filed: December 2, 2018
    Date of Patent: March 3, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu
  • Patent number: 10575464
    Abstract: A fixed-line trimmer head for a rotary trimmer device includes the upper portion having a periphery, wherein the upper portion has a plurality of openings spaced from the periphery; and a plurality of mechanisms. Each mechanism can hold a strip of line and includes a post portion disposed through one of the openings in the upper portion, and a flange disposed at one end of the post portion and sandwiched between the upper portion and lower portion of the trimmer head to prevent vertical movement of the mechanism. The post portion includes two line channels, each line channel defining a passageway to receive the same strip of line, wherein at least one of the line channels is curved such that any portion of the strip of line being received through the passageway of that line channel is bent at that portion of the strip of line away from the second line channel while passing through that at least one line channel that is curved.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: March 3, 2020
    Assignee: Shakespeare Company, LLC
    Inventors: David B. Skinner, Wen Liu
  • Patent number: 10568551
    Abstract: A hearing diagnosis device and a hearing diagnosis method are provided. The device includes a storage unit, an otoacoustic emission detecting module, and a hearing diagnosis management module. The storage unit stores a hearing diagnosis image sample database and a hearing information sample database. The otoacoustic emission detecting module is configured to perform an otoacoustic emission detecting operation by playing a test audio to an ear of a user to obtain a first hearing diagnosis image corresponding to the ear. The hearing diagnosis management module is configured to perform a hearing diagnosis operation according to the first hearing diagnosis image, a plurality of hearing diagnosis image samples of the hearing diagnosis image sample database, and a plurality of hearing information samples, respectively corresponding to the hearing diagnosis image samples, of the hearing information sample database, so as to determine first hearing information of the ear.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: February 25, 2020
    Assignee: National Tsing Hua University
    Inventors: Hau-Tieng Wu, Pa-Chun Wang, Yi-Wen Liu
  • Publication number: 20200059778
    Abstract: This application relates to the field of communications technologies, and in particular, to a profile download technology. In a profile download method, a primary device obtains an embedded integrated circuit card identifier (EID) of a secondary device, where the EID is used by the primary device to obtain, from a mobile operator server, profile download information that matches the EID; receives the profile download information from the mobile operator server; and sends the profile download information to the secondary device, where the profile download information is used by the secondary device to download a profile from a profile management server, and the profile is installed in an embedded UICC (eUICC) of the secondary device after the download is complete.
    Type: Application
    Filed: June 13, 2017
    Publication date: February 20, 2020
    Inventors: Feng LI, Wen LIU, Chunlai FENG, Tao LI, Xiaolin LI, Xutao GAO, Wenhua LI
  • Publication number: 20200054984
    Abstract: Disclosed is a flue gas purification tower, comprising a tower body, at least one gas inlet (1) disposed at the bottom of the tower body, at least one gas outlet (2) disposed at the top of the tower body, at least one active coke layer (3) located inside the tower body, and a baffle plate (4) arranged in a place where the flow direction of the flue gas from the gas inlet changes. The baffle plate (4) is a straight plate, an arc plate, a straight-and-arc plate or a straight-arc-straight plate, wherein the straight-and-arc plate comprises a straight segment and an arc segment connected with each other; and the straight-arc-straight plate comprises a straight segment in the vertical direction, a straight segment in the horizontal direction, and an arc segment connected between the two straight segments.
    Type: Application
    Filed: November 23, 2016
    Publication date: February 20, 2020
    Applicant: INSTITUTE OF PROCESS ENGINEERING, CHINESE ACADEMY OF SCIENCES
    Inventors: Tingyu Zhu, Yuran Li, Shuai Zhang, Wen Liu
  • Patent number: 10564752
    Abstract: A gate driver and a touch display apparatus thereof are provided. The gate driver includes a plurality of shift registers and at least one loop circuit. The shift registers provide multiple gate signals to a touch display module. The loop circuit is coupled in series with the shift registers and receives at least one touch switching signal to set a loop time of the loop circuit. The touch display module performs at least one touch scan during the loop time.
    Type: Grant
    Filed: April 1, 2018
    Date of Patent: February 18, 2020
    Assignee: Au Optronics Corporation
    Inventors: Chi-Cheng Chen, Gui-Wen Liu
  • Patent number: 10566279
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: February 18, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen-Long Lu, Jen-Kuang Fang, Min Lung Huang, Chan Wen Liu, Ching Kuo Hsu
  • Publication number: 20200049651
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Fen CHEN, Jeffrey P. GAMBINO, Carole D. GRAAS, Wen LIU, Prakash PERIASAMY
  • Publication number: 20200051821
    Abstract: Semiconductor structures and methods for forming the same are provided. The method includes forming a dummy gate structure and forming a spacer on a lower portion of a sidewall of the dummy gate structure and exposing an upper portion of the sidewall of the dummy gate structure. The method further includes forming a dielectric layer covering the upper portion of the sidewall of the dummy gate structure exposed by the spacer and removing the dummy gate structure to form a tube-shaped trench. The method further includes removing a portion of the dielectric layer to form a cone-shaped trench and forming a gate structure in a bottom portion of the tube-shaped trench. The method further includes forming a hard mask structure in the cone-shaped trench and an upper portion of the tube-shaped trench, and an interface between the hard mask structure and the dielectric layer overlaps the spacer.
    Type: Application
    Filed: October 8, 2019
    Publication date: February 13, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsin-Ying LIN, Mei-Yun WANG, Hsien-Cheng WANG, Fu-Kai YANG, Shih-Wen LIU, Hsiao-Chiu HSU
  • Publication number: 20200051988
    Abstract: A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.
    Type: Application
    Filed: October 17, 2019
    Publication date: February 13, 2020
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • Patent number: 10559560
    Abstract: The present disclosure provides a semiconductor ESD protection device. The semiconductor ESD protection device includes a substrate including a first conductivity type, a gate formed on the substrate, a source region and a drain region formed in the substrate, and a body region formed in the substrate. The substrate and the body region include a first conductivity type. The source region and the drain region include a second conductivity type. And the first conductivity type and the second conductivity type are complementary to each other. The body region is electrically connected to the gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 11, 2020
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu, Wei-Ming Liao