Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Dynamic crossband link method and wireless extender
    Patent number: 10405255
    Abstract: A dynamic crossband link method is provided, which includes utilizing a local forwarding module to transmit and receive packet data to and from a client device via a first frequency band; obtaining a plurality of communication quality indicators corresponding to a plurality of uplink forwarding modules; and determining to transmit the packet data to a wireless access device and receive the packet data from the wireless access device via one of the plurality of uplink forwarding modules according to the plurality of communication quality indicators.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 3, 2019
    Assignee: U-MEDIA Communications, Inc.
    Inventors: Chia-Ching Huang, Yi-Wen Liu
  • Pivot posts and trimmer heads utilizing the same
    Patent number: 10398078
    Abstract: A trimmer head having at least two pivoting line holders for holding multiple folded strips of trimming line is presented wherein said pivoting line holders are retained within said housing between said housing and said cover and extend upward through apertures in said cover, said line holders being capable of movement around a vertical axis of rotation, at least three embodiments are disclosed which provide a rounded landing for supporting the inner radius of a folded strip of trimming line, the rounded geometry of the landing prevents line stress and breakage, the various embodiments include a pivot post having two parallel straight through holes with a rounded vertical wall between the through holes, a single open passageway having a center metal post, and a single open passageway having a series of at least two metal pins through the center of the passageway.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: September 3, 2019
    Assignee: Shakespeare Company, LLC
    Inventors: David B. Skinner, Brian Searfoss, Wen Liu, Lin Wang, Jack Yang
  • 3D Capacitor and Method of Manufacturing Same
    Publication number: 20190252519
    Abstract: A three-dimensional (3D) capacitor includes a semiconductor substrate; one or more fins extending from the semiconductor substrate; an insulator material between each of the one or more fins; a dielectric layer over a first portion of the one or more fins and over the insulator material; a first electrode over the dielectric layer; spacers on sidewalls of the first electrode; and a second electrode over a second portion of the one or more fins and over the insulator material, wherein the first and second portions are different.
    Type: Application
    Filed: April 25, 2019
    Publication date: August 15, 2019
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • MOISTURE DETECTION AND INGRESSION MONITORING SYSTEMS AND METHODS OF MANUFACTURE
    Publication number: 20190250116
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Application
    Filed: April 23, 2019
    Publication date: August 15, 2019
    Inventors: Fen CHEN, Jeffrey P. GAMBINO, Carole D. GRAAS, Wen LIU, Prakash PERIASAMY
  • SEMICONDUCTOR ARRANGEMENT AND FORMATION THEREOF
    Publication number: 20190252265
    Abstract: A semiconductor arrangement and method of forming the same are described. A semiconductor arrangement includes a third metal connect in contact with a first metal connect in a first active region and a second metal connect in a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes forming a first opening over the first metal connect, the STI region, and the second metal connect, and forming the third metal connect in the first opening. Forming the third metal connect over the first metal connect and the second metal connect mitigates RC coupling.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: I-Wen WU, Hsien-Cheng Wang, Mei-Yun Wang, Shih-Wen Liu, Chao-Hsun Wang, Yun Lee
  • Video file playback system capable of previewing image, method thereof, and computer program product
    Patent number: 10382717
    Abstract: A video file playback system capable of previewing an image, a method thereof, and a computer program product can sequentially compare change amounts between chronological two of frame images, select the frame images, of which the change amounts exceed a preset value, in at least one time interval, and select a frame image, which has a maximum change amount, in the frame images in each time interval as a preview image. By displaying a preview image corresponding to each time interval, a user can quickly browse key images of each time interval.
    Type: Grant
    Filed: November 9, 2016
    Date of Patent: August 13, 2019
    Assignee: VIVOTEK INC.
    Inventors: Chien-Wen Liu, Yen-Fu Lin, Shih-Wu Fanchiang
  • Passivated and faceted for fin field effect transistor
    Patent number: 10381482
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • DRAM and method of operating the same in an hierarchical memory system
    Patent number: 10380024
    Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.
    Type: Grant
    Filed: January 2, 2018
    Date of Patent: August 13, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • FLUOROPOLYETHER COMPOUND AND LUBRICANT
    Publication number: 20190237101
    Abstract: Fluoropolyether compounds that can be used as a lubricant, such as for magnetic recording media. The compounds have a terminal group that includes a phenol or benzene. The fluoropolyether compounds reduce the head to media distance while keeping comparable reliability in a hard disk drive compared to current industrial widely used fluoropolyether based lubricants.
    Type: Application
    Filed: January 29, 2019
    Publication date: August 1, 2019
    Inventors: Yu Lu, JiPing Yang, Jingyuan Zhuo, Qian Guo, Wen Liu
  • PACKAGE DEVICE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING THE PACKAGE DEVICE
    Publication number: 20190229054
    Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.
    Type: Application
    Filed: January 25, 2018
    Publication date: July 25, 2019
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wen-Long LU, Jen-Kuang FANG, Min Lung HUANG, Chan Wen LIU, Ching Kuo HSU
  • Using metal-containing layer to reduce carrier shock in package formation
    Patent number: 10354988
    Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Yi-Jou Lin
  • FINFETs with wrap-around silicide and method forming the same
    Patent number: 10355137
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: July 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • DRAM and method for determining binary logic using a test voltage level
    Patent number: 10354713
    Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: July 16, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • IC WAFER FOR IDENTIFICATION OF CIRCUIT DIES AFTER DICING
    Publication number: 20190214348
    Abstract: Aspects of the present disclosure provide an integrated circuit (IC) wafer having a plurality of circuit dies each bounded by a set of scribe lines. The IC structure includes: a plurality of reference features each respectively positioned in a first layer of one of the plurality of circuit dies. The reference feature of each circuit die is equidistant from a respective set of scribe lines for the circuit die, and a plurality of identification features each positioned in a second layer of one of the plurality of circuit dies. The reference feature of each circuit die has a distinct offset vector indicative of a positional difference between the identification feature for the circuit die and the reference feature for the circuit die, relative to the identification feature of each other circuit die.
    Type: Application
    Filed: January 10, 2018
    Publication date: July 11, 2019
    Inventors: Wen Liu, Sebastian T. Ventrone, Adam C. Smith, Janice M. Adams, Nazmul Habib
  • Integrated fan-out packages
    Patent number: 10347574
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Grant
    Filed: January 22, 2018
    Date of Patent: July 9, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Oral Irrigator
    Publication number: 20190201175
    Abstract: An oral irrigator contains: a body, a water tank and a detachable jet tip which are both in connection with the body, a power device and a control device Which are both accommodated in the body. The power device is configured to deliver water from the water tank to the detachable jet tip. The power device includes a first outlet defined thereon and configured to discharge the water, a delivery tube connecting with the first outlet, and a first seal element configured to stop water flowing into the body from the power device so that the water discharges out of the first outlet.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Jin-Feng Li, Gang Wang, Qing Zhang, Xin-Quan Liu, Xiao-Wen Liu
  • Negative Capacitance Field Effect Transistor
    Publication number: 20190207035
    Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.
    Type: Application
    Filed: March 14, 2019
    Publication date: July 4, 2019
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
  • Method of forming a fin structure of semiconductor device
    Patent number: 10340191
    Abstract: A method of forming a fin structure of a semiconductor device, such as a fin field effect transistor (FinFET) is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: July 2, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • System and method for preserving data in volatile memory
    Patent number: 10338831
    Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: July 2, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Semiconductor device having stressor layer
    Patent number: 10340383
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Grant
    Filed: September 27, 2016
    Date of Patent: July 2, 2019
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Huang-Siang Lan, CheeWee Liu, Chi-Wen Liu, Shih-Hsien Huang, I-Hsieh Wong, Hung-Yu Yeh, Chung-En Tsai