Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnection structure, fabricating method thereof, and semiconductor device using the same
    Patent number: 10483208
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Metal gate stack having TaAlCN layer
    Patent number: 10483112
    Abstract: Gate stacks for improving integrated circuit device performance and methods for fabricating such gate stacks are disclosed herein. An exemplary method includes forming a gate stack over a substrate and at least partially removing the gate stack, thereby forming an opening. A multi-function layer is deposited in the opening and a work function layer is deposited over the multi-function layer. The multi-function layer includes nitrogen and one of titanium or tantalum. The work function layer includes nitrogen and one of titanium or tantalum. A concentration of the nitrogen of the work function layer is different than a concentration of the nitrogen of the multi-function layer. In some implementations, the concentration of the nitrogen of the work function layer from about 2% to about 5% and the concentration of the nitrogen of the multi-function layer from about 5% to about 15%.
    Type: Grant
    Filed: July 23, 2018
    Date of Patent: November 19, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Vertical gate all around (VGAA) devices and methods of manufacturing the same
    Patent number: 10483367
    Abstract: Vertical gate all around (VGAA) devices and methods of manufacture thereof are described. A method for manufacturing a VGAA device includes: exposing a top surface and sidewalls of a first portion of a protrusion extending from a doped region, wherein a second portion of the protrusion is surrounded by a gate stack; and enlarging the first portion of the protrusion using an epitaxial growth process.
    Type: Grant
    Filed: January 16, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Hao Chang, Ming-Shan Shieh, Cheng-Long Chen, Chin-Chi Wang, Chi-Wen Liu, Wai-Yi Lien, Chih-Hao Wang
  • ACYLATED INSULIN COMPOUND
    Publication number: 20190345215
    Abstract: The presently described compounds relate to the treatment of diabetes and/or hyperglycemia. More particularly, the described compounds relate to acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 14, 2019
    Inventors: Wen Liu, Adam Robert Mezo, Francisco Alcides Valenzuela
  • Mechanisms for semiconductor device structure
    Patent number: 10468257
    Abstract: Semiconductor device structures and methods for forming the same are provided. The method for forming a semiconductor device structure includes forming a dummy gate structure over a substrate and forming a dielectric layer over the substrate around the dummy gate structure. The method for forming a semiconductor device structure further includes removing the dummy gate structure and removing a portion of the dielectric layer to form a funnel shaped trench. The method for forming a semiconductor device structure further includes forming a gate structure in a bottom portion of the funnel shaped trench and filling a hard mask material in a top portion of the funnel shaped trench to form a funnel shaped hard mask structure.
    Type: Grant
    Filed: August 18, 2016
    Date of Patent: November 5, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Ying Lin, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Shih-Wen Liu, Audrey Hsiao-Chiu Hsu
  • Semiconductor device and manufacturing method thereof
    Patent number: 10468504
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: November 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Graphically managing data classification workflows in a social networking system with directed graphs
    Patent number: 10459979
    Abstract: Various embodiments include a classification platform system. A user can define a classification experiment on the classification platform system. For example, the user can define an input data space by selecting at least one of data sources interfaced with the classification platform system and defining a workflow configuration including a directed graph (DG) connecting a plurality of transformation blocks to represent an experiment workflow. The DG can specify how one or more outputs of each of the transformation blocks are fed into one or more other transformation blocks. The DG can be defined graphically. The classification platform system can schedule the experiment workflow to be executed on a distributed computation platform according to the input data space and the workflow configuration.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 29, 2019
    Assignee: Facebook, Inc.
    Inventors: Szymon Piechowicz, Barak Reuven Naveh, Annie Hsin-Wen Liu, Ashish Gupta
  • FIELD-EFFECT TRANSISTORS HAVING CONTACTS TO 2D MATERIAL ACTIVE REGION
    Publication number: 20190326399
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Application
    Filed: May 6, 2019
    Publication date: October 24, 2019
    Inventors: Ling-Yen YEH, Yee-Chia YEO, Chi-Wen LIU
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    Publication number: 20190326437
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
  • Method of manufacturing a semiconductor device including a ternary alloy layer formed by a microwafe anneal process
    Patent number: 10453688
    Abstract: A method of manufacturing a semiconductor device includes forming a first metal layer on a semiconductor substrate and forming a second metal layer on the first metal layer. The second metal layer is formed of a different metal than the first metal layer. Microwave radiation is applied to the semiconductor substrate, first metal layer, and second metal layer to form an alloy including components of the first metal layer, second metal layer, and the semiconductor substrate.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: October 22, 2019
    Assignees: National Chiao Tung University, Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chung-Chun Hsu, Wei-Chun Chi
  • Hybrid memory system and method of operating the same
    Patent number: 10437499
    Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: October 8, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • EARPHONE DEVICE
    Publication number: 20190289387
    Abstract: The invention discloses an earphone device comprising a first case, a first speaker unit, a first recording unit, and a second recording unit. The first speaker unit, disposed inside the first case, emits a first testing sound signal according to a test command. The first recording unit, disposed inside the first case, records a first environment sound signal according to a record command or a noise cancelling command. The second recording unit, disposed inside the first case, records a first feedback sound signal, related to the first testing sound signal, according to the test command.
    Type: Application
    Filed: March 12, 2019
    Publication date: September 19, 2019
    Inventors: Peng LEE, Yi-Wen LIU
  • FORMING GATE LINE-END OF SEMICONDUCTOR STRUCTURES
    Publication number: 20190287852
    Abstract: The current disclosure provides a semiconductor fabrication method that defines the height of gate structures at the formation of the gate structure. A gate line-end region is formed by removing a portion of a gate structure. A resulted recess is filled with a dielectric material is chosen to have a material property suitable for a later contact formation process of forming a metal contact. A metal contact structure is formed through the recess filling dielectric layer to connect to a gate structure and/or a source/drain region.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Che-Liang Chung, Che-Hao Tu, KEI-WEI CHEN, Chih-Wen Liu, You-Shiang Lin, Yi-Ching Liang
  • Diode structure and electrostatic discharge protection device including the same
    Patent number: 10418356
    Abstract: The present disclosure provides a diode structure and an electrostatic discharge (ESD) protection circuit including the same. The diode structure includes a P-type substrate. The diode structure further includes a plurality of wavy N-doping regions formed on the P-type substrate. Each of the wavy N-doping regions extends in a first direction and has an N-doping width in a second direction perpendicular to the first direction. The diode structure further includes a plurality of wavy P-doping regions formed on the P-type substrate. Each of the wavy P-doping regions extends in the first direction and has a P-doping width in the second direction. The N-doping widths are essentially identical at different positions along the first direction, and the P-doping widths are essentially identical at different positions along the first direction.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: September 17, 2019
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Fang-Wen Liu, Tseng-Fu Lu
  • Method of fabricating a semiconductor device having modified profile metal gate
    Patent number: 10418456
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Grant
    Filed: June 5, 2017
    Date of Patent: September 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Wen Liu, Clement Hsingjen Wann, Ming-Huan Tsai, Zhao-Cheng Chen
  • Self-heat preservation building structure
    Patent number: 10415235
    Abstract: The present utility model relates to a building structure, and in particular to a self-heat preservation building structure applied to extremely severe cold regions.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: September 17, 2019
    Assignee: Feng He Ying Zao Group Co., Ltd.
    Inventors: Baoru Jie, Jiangang Jie, Hongyang Xie, Zhihui Yao, Shuangxi Zhou, Sheng Qian, Yuchun Chen, Wujin Tao, Wen Liu, Xin He, Luolong Zhan
  • Pressure sensing device
    Patent number: 10416031
    Abstract: A pressure sensing mat may include: a first substrate; a second substrate disposed opposite to the first substrate; a first electrode layer disposed on a side of the first substrate that faces the second substrate, the first electrode layer comprising a plurality of first electrode patterns; a second electrode layer disposed on a side of the second substrate that faces the first substrate, the second electrode layer comprising a plurality of second electrode patterns; and a spacer layer disposed between the first substrate and the second substrate and comprising a plurality of holes such that the first electrode patterns are configured to contact the second electrode patterns through the holes.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: September 17, 2019
    Assignee: MedicusTek, Inc.
    Inventors: Chia-Ming Hsu, Chung-Chih Lin, Chi Wen Liu, Chun Lin, Chao-Hung Chou
  • Engagement structure for tool
    Publication number: 20190275646
    Abstract: An engagement structure for a tool contains: a drive member. The drive member includes an accommodation orifice defined in the drive member, a hexagonal tooth portion formed around the accommodation orifice, and six arcuately concave sections respectively arranged on six sides of the hexagonal tooth portion. Each of the six arcuately concave sections is arranged on a center of each of the six sides of the hexagonal tooth portion. The drive member further includes multiple bevel rims, any two spaced of the multiple bevel rims respectively extend from two sides of each arcuately concave sections, and any adjacent of the multiple bevel rims connect, wherein an inclined angle each of the multiple bevel rims is 2 degrees.
    Type: Application
    Filed: March 12, 2018
    Publication date: September 12, 2019
    Inventor: Ben Wen LIU
  • INTERCONNECTION STRUCTURE, FABRICATING METHOD THEREOF, AND SEMICONDUCTOR DEVICE USING THE SAME
    Publication number: 20190279939
    Abstract: A semiconductor device includes a semiconductor substrate, a contact region present in the semiconductor substrate, and a silicide present on a textured surface of the contact region. A plurality of sputter ions is present between the silicide and the contact region. Since the surface of the contact region is textured, the contact area provided by the silicide is increased accordingly, thus the resistance of a interconnection structure in the semiconductor device is reduced.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 12, 2019
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Acylated insulin compound
    Patent number: 10400021
    Abstract: The presently described compounds relate to the treatment of diabetes and/or hyperglycemia. More particularly, the described compounds relate to acylated insulin compounds that lower blood glucose, pharmaceutical compositions containing such compounds, therapeutic uses of such compounds, and an intermediate compound used to make the acylated insulin compounds.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: September 3, 2019
    Assignee: Eli Lilly and Company
    Inventors: Wen Liu, Adam Robert Mezo, Francisco Alcides Valenzuela