Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10558714
    Abstract: An online system ranks topic-groups for users and presents content items in topic-based feeds. A topic group corresponds to one or more topic(s) and can be used to generate a feed for presenting the content items related to the topic(s). For a particular user, the topic groups are ranked according to the likelihood of the user interacting with content items included in the topic groups. The topic groups are ranked using information of the users and/or users' historical interaction data such as click-based interaction data, post-based interaction data, or engagement-based interaction data. The online system generates and provides a user interface for presenting the topic groups to the client device. Content items that are related to the topic(s) corresponding to the topic group are presented in each topic-based feed such that the user can switch between different topic-based feeds.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: February 11, 2020
    Assignee: Facebook, Inc.
    Inventors: Shengbo Guo, Annie Hsin-Wen Liu, David Vickrey, Khalid Bakry El-Arini
  • Publication number: 20200044088
    Abstract: A device includes a first semiconductor strip, a first gate dielectric encircling the first semiconductor strip, a second semiconductor strip overlapping the first semiconductor strip, and a second gate dielectric encircling the second semiconductor strip. The first gate dielectric contacts the first gate dielectric. A gate electrode has a portion over the second semiconductor strip, and additional portions on opposite sides of the first and the second semiconductor strips and the first and the second gate dielectrics.
    Type: Application
    Filed: October 11, 2019
    Publication date: February 6, 2020
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20200035564
    Abstract: A semiconductor device includes a substrate, a first insulating structure, a second insulating structure, at least one first active semiconductor fin, and at least one second active semiconductor fin. The first insulating structure and the second insulating structure are disposed on the substrate. The first active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the first insulating structure. The second active semiconductor fin is disposed on the substrate and has a protruding portion protruding from the second insulating structure. The protruding portion of the first active semiconductor fin and the protruding portion of the second active semiconductor fin have different heights.
    Type: Application
    Filed: October 4, 2019
    Publication date: January 30, 2020
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Patent number: 10545111
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy
  • Patent number: 10545110
    Abstract: Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: January 28, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Fen Chen, Jeffrey P. Gambino, Carole D. Graas, Wen Liu, Prakash Periasamy
  • Publication number: 20200027963
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: September 26, 2019
    Publication date: January 23, 2020
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • Publication number: 20200026957
    Abstract: Techniques are described that facilitate automatically distinguishing between different expressions of a same or similar emotion. In one embodiment, a computer-implemented is provided that comprises partitioning, by a device operatively coupled to a processor, a data set comprising facial expression data into different clusters of the facial expression data based on one or more distinguishing features respectively associated with the different clusters, wherein the facial expression data reflects facial expressions respectively expressed by people. The computer-implemented method can further comprise performing, by the device, a multi-task learning process to determine a final number of the different clusters for the data set using a multi-task learning process that is dependent on an output of an emotion classification model that classifies emotion types respectively associated with the facial expressions.
    Type: Application
    Filed: September 30, 2019
    Publication date: January 23, 2020
    Inventors: Feng Jin, Wen Liu, Yong Qin, Qin Shi, Peng Wang, Shi Lei Zhang
  • Patent number: 10533906
    Abstract: A pressure sensing array includes a plurality of pressure sensing units and a control unit. Each of the pressure sensing units includes a plurality of first electrode blocks and a plurality of second electrode blocks. The second electrode blocks are arranged in a staggered manner along a first direction or a second direction, in which the first direction is substantially perpendicular to the second direction. The control unit is coupled to the pressure sensing units and used for controlling the first electrode blocks and the second electrode blocks of the each of the pressure sensing units to be turned on or off respectively.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 14, 2020
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Chi-Cheng Chen, Gui-Wen Liu
  • Patent number: 10532628
    Abstract: An HVAC module having a reconfigurable bi-level duct system is disclosed. The air duct includes an air duct inlet in fluid communication with the HVAC module, an interior wall dividing the air duct into first and second air passageways, a bypass port enabling fluid communication between the first air and second air passageways. A downstream control valve disposed adjacent the bypass port and is configured to selectively direct air flow from one of the first and second air passageways to the other of the first and second air passageways. An upstream flow control valve is disposed adjacent to the inlet of the air duct, wherein the upstream flow control valve is configured to selectively direct air flow from the hot and cold chambers of the HVAC module to the first and second air passageways of the air duct.
    Type: Grant
    Filed: May 5, 2015
    Date of Patent: January 14, 2020
    Assignee: MAHLE International GmbH
    Inventors: Mingyu Wang, Yanping Xia, Wen Liu, Prasad S. Kadle, Jeffrey C. Kinmartin
  • Patent number: 10535732
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: January 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20200013707
    Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.
    Type: Application
    Filed: July 7, 2019
    Publication date: January 9, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu Jeng, Dai-Jang Chen, Hsiang-Tai Lu, Hsien-Wen Liu, Chih-Hsien Lin, Shih-Ting Hung, Po-Yao Chuang
  • Publication number: 20200013869
    Abstract: A semiconductor device has a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is disposed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is less than the first height.
    Type: Application
    Filed: September 16, 2019
    Publication date: January 9, 2020
    Inventors: Yu-Lien HUANG, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN
  • Publication number: 20200013719
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Application
    Filed: September 19, 2019
    Publication date: January 9, 2020
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Patent number: 10529671
    Abstract: Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.
    Type: Grant
    Filed: July 3, 2017
    Date of Patent: January 7, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsiao-Wen Lee, Hsien-Wen Liu, Shin-Puu Jeng
  • Publication number: 20200006234
    Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Hsien-Wen Liu, Po-Yao Chuang, Feng-Cheng Hsu, Po-Yao Lin
  • Publication number: 20200006164
    Abstract: In an embodiment, a method includes: stacking a plurality of first dies to form a device stack; revealing testing pads of a topmost die of the device stack; testing the device stack using the testing pads of the topmost die; and after testing the device stack, forming bonding pads in the topmost die, the bonding pads being different from the testing pads.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Chen-Hua Yu, Sung-Feng Yeh, Ming-Fa Chen, Hsien-Wei Chen, Hui-Wen Liu, Ching-Pin Yuan
  • Publication number: 20200006498
    Abstract: A semiconductor device includes a substrate, at least one semiconductor fin, and at least one epitaxy structure. The semiconductor fin is present on the substrate. The semiconductor fin has at least one recess thereon. The epitaxy structure is present in the recess of the semiconductor fin. The epitaxy structure includes a topmost portion, a first portion and a second portion arranged along a direction from the semiconductor fin to the substrate. The first portion has a germanium atomic percentage higher than a germanium atomic percentage of the topmost portion and a germanium atomic percentage of the second portion.
    Type: Application
    Filed: September 13, 2019
    Publication date: January 2, 2020
    Inventors: Chia-Ming Chang, Chi-Wen Liu, Cheng-Chien Li, Hsin-Chieh Huang
  • Patent number: 10522640
    Abstract: Gate structures and methods of forming the gate structures are described. In some embodiments, a method includes forming source/drain regions in a substrate, and forming a gate structure between the source/drain regions. The gate structure includes a gate dielectric layer over the substrate, a work function tuning layer over the gate dielectric layer, a first metal over the work function tuning layer, an adhesion layer over the first metal, and a second metal over the adhesion layer. In some embodiments, the adhesion layer can include an alloy of the first and second metals, and may be formed by annealing the first and second metals. In other embodiments, the adhesion layer can include an oxide of at least one of the first and/or second metal, and may be formed at least in part by exposing the first metal to an oxygen-containing plasma or to a natural environment.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko JangJian, Chi-Wen Liu, Chih-Nan Wu, Chun Che Lin
  • Patent number: 10521945
    Abstract: According to an embodiment of the present invention, a computer-implemented method for modeling text-to-articulatory movement conversion is provided. In the method, text features are generated for a plurality of texts, wherein the text feature comprises a phoneme. Articulatory features are determined for the plurality of texts from a plurality of audio signals and a plurality of visual signals, wherein the audio signals record speeches of the plurality of texts, the visual signals record three-dimensional images of an articulator when speaking the plurality of texts, and the articulatory features indicate articulatory positions of the articulator in the speeches. A text-to-articulatory movement model is established with the text features as inputs and the articulatory features as outputs.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: December 31, 2019
    Assignee: International Business Machines Corporation
    Inventors: Wen Liu, Qin Shi, Shi Lei Zhang, Peng Cheng Zhu
  • Publication number: 20190393111
    Abstract: A power device package structure including a first substrate, a second substrate, at least one power device, and a package is provided. A heat conductivity of the first substrate is greater than 200 Wm?1K?1. The power device is disposed on the first substrate, and the second substrate is disposed under the first substrate. A heat capacity of the second substrate is greater than that of the first substrate. The package encapsulates the first substrate, the second substrate, and the power device.
    Type: Application
    Filed: September 7, 2018
    Publication date: December 26, 2019
    Applicant: ACTRON TECHNOLOGY CORPORATION
    Inventors: Hsin-Chang Tsai, Ching-Wen Liu