Patents by Inventor Wen Liu

Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • FOLDING DEVICE
    Publication number: 20160179142
    Abstract: A folding device provides a top case having magnetic elements at a top magnetic section and a bottom case having a groove and magnetic elements around the groove at a bottom magnetic section. As the top magnetic section of the top case is disposed at the bottom magnetic section of the bottom case, the top case is configurable at one of a folded position and at least two opened positions with respect to the bottom case. When the top case is at the first opened position, a first stopper and a first magnetic element at the groove of the bottom magnetic section maintain the top case at the first opened position; when the top case is at the second opened position, a second stopper and a second magnetic element at the groove of the bottom magnetic section maintain the top case at the second opened position.
    Type: Application
    Filed: October 12, 2015
    Publication date: June 23, 2016
    Inventors: Chen-Yi Liang, Che-Wen Liu
  • Isolation Structure of Fin Field Effect Transistor
    Publication number: 20160172470
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Application
    Filed: February 5, 2016
    Publication date: June 16, 2016
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Substituted pyrazoles and uses thereof
    Patent number: 9365583
    Abstract: The present invention provides for compounds of formula 0 and various embodiments thereof, and compositions comprising compounds of formula 0 and various embodiments thereof. In compounds of formula 0, the groups R1A, R1B, R1C, R1D, R2, R3, R4, R5 and R6 have the meaning as described herein. The present invention also provides for methods of using compounds of formula 0 and compositions comprising compounds of formula 0 as DLK inhibitors and for treating neurodegeneration diseases and disorders.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: June 14, 2016
    Assignee: Genentech, Inc.
    Inventors: Michael Siu, Anthony Estrada, Wen Liu, Joseph P. Lyssikatos, Snahel Patel, Guibai Liang, Kevin Chen
  • FETs and methods for forming the same
    Patent number: 9362386
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 7, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20160155846
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • FinFETs and methods for forming the same
    Patent number: 9349841
    Abstract: A finFET and methods for forming a finFET are disclosed. A structure comprises a substrate, a fin, a gate dielectric, and a gate electrode. The substrate comprises the fin. The fin has a major surface portion of a sidewall, and the major surface portion comprises at least one lattice shift. The at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the sidewall. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: February 19, 2015
    Date of Patent: May 24, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • FABRICATION METHOD OF SEMICONDUCTOR PACKAGE HAVING EMBEDDED SEMICONDUCTOR ELEMENTS
    Publication number: 20160141281
    Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.
    Type: Application
    Filed: October 2, 2015
    Publication date: May 19, 2016
    Inventors: Yan-Heng Chen, Chun-Tang Lin, Yan-Yi Liao, Hung-Wen Liu, Chieh-Yuan Chi, Hsi-Chang Hsu
  • PACKAGE STRUCTURE AND FABRICATION METHOD THEREOF
    Publication number: 20160141227
    Abstract: A method for fabricating a package structure is provided, which includes: providing a first carrier having a circuit layer thereon; forming a plurality of conductive posts on the circuit layer and disposing at least an electronic element on the first carrier; forming an encapsulant on the first carrier to encapsulate the conductive posts, the circuit layer and the electronic element; and removing the first carrier, thereby dispensing with the conventional hole opening process for forming the conductive posts and hence reducing the fabrication costs.
    Type: Application
    Filed: November 13, 2015
    Publication date: May 19, 2016
    Inventors: Chun-Tang Lin, Shih-Ching Chen, Yi-Che Lai, Hong-Da Chang, Hung-Wen Liu, Yi-Wei Liu, Hsi-Chang Hsu
  • PACKAGE STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20160135299
    Abstract: A method of fabricating a package structure is provided, including forming a plurality of openings by removing a portion of the material on one side of a conductive layer, forming an insulating material as an insulating layer in the openings, removing a portion of the material on the other side of the conductive layer to serve as a wiring layer, disposing an electronic component on the wiring layer, and forming an encapsulating layer to cover the electronic component, thereby allowing the single wiring layer to be connected to the electronic component on one side and connected to solder balls on the other side thereof to shorten the signal transmission path. The present invention further provides a package structure thus fabricated.
    Type: Application
    Filed: July 16, 2015
    Publication date: May 12, 2016
    Inventors: Shih-Ping Hsu, Chin-Wen Liu, Tang-I Wu, Shu-Wei Hu
  • Multilayer Composite Conductor and Manufacturing Method Thereof
    Publication number: 20160133353
    Abstract: A multilayer composite conductor comprises an inner layer and an outer layer. The inner layer comprises at least one wire which has a conductivity of 60% to 70% IACS as a core of the multilayer composite conductor; wherein a volume of the inner layer is 40% to 55% of a total volume of the multilayer composite conductor; and the outer layer comprises multiple wires which have a conductivity of 70% to 98% IACS, and the outer layer is wound around the inner layer; wherein a volume of the outer layer is 45% to 60% of the total volume of the multilayer composite conductor. In another aspect, the present invention also provides a method for manufacturing a multilayer composite conductor. At the same current-carrying surface, the multilayer composite conductor of the present invention saves more than 60% of copper usage, thereby achieving light weight and low cost.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 12, 2016
    Inventors: Li-Wen Liu, Wei-Jen Liu
  • Metal gate stack having TaAlCN layer
    Patent number: 9337192
    Abstract: An integrated circuit device includes a semiconductor substrate; and a gate stack disposed over the semiconductor substrate. The gate stack further includes a gate dielectric layer disposed over the semiconductor substrate; a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer comprises tantalum aluminum carbon nitride (TaAlCN); a work function layer disposed over the multi-function blocking/wetting layer; and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Ting-Chun Wang, Chi-Cherng Jeng, Chi-Wen Liu
  • Semiconductor device including a semiconductor sheet unit interconnecting a source and a drain
    Patent number: 9337263
    Abstract: A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed.
    Type: Grant
    Filed: June 24, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Jiun-Peng Wu, Tetsu Ohtou, Ching-Wei Tsai, Chih-Hao Wang, Chi-Wen Liu
  • Metal gate stack having TiAICN as work function layer and/or blocking/wetting layer
    Patent number: 9337303
    Abstract: A metal gate stack having a titanium aluminum carbon nitride (TiAlCN) as a work function layer and/or a multi-function blocking/wetting layer, and methods of manufacturing the same, are disclosed. In an example, an integrated circuit device includes a semiconductor substrate and a gate stack disposed over the semiconductor substrate. The gate stack includes a gate dielectric layer disposed over the semiconductor substrate, a multi-function blocking/wetting layer disposed over the gate dielectric layer, wherein the multi-function blocking/wetting layer includes TiAlCN, a work function layer disposed over the multi-function blocking/wetting layer, and a conductive layer disposed over the work function layer.
    Type: Grant
    Filed: July 10, 2014
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shiu-Ko Jangjian, Chi-Wen Liu, Chi-Cherng Jeng, Ting-Chun Wang
  • FinFET with dummy gate on non-recessed shallow trench isolation (STI)
    Patent number: 9337318
    Abstract: An embodiment fin field effect transistor (FinFET) device includes fins formed from a semiconductor substrate, a non-recessed shallow trench isolation (STI) region disposed between the fins, and a dummy gate disposed on the non-recessed STI region.
    Type: Grant
    Filed: October 26, 2012
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Semiconductor device having a carbon containing insulation layer formed under the source/drain
    Patent number: 9331173
    Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Shih-Wen Liu, Mei-Yun Wang, Hsien-Cheng Wang, Fu-Kai Yang, Hsiao-Chiu Hsu, Hsin-Ying Lin
  • Metal gate and gate contact structure for FinFET
    Patent number: 9331179
    Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards, forming a fin, a gate dielectric over a top surface and sidewalls of the fin, a liner overlaying the gate dielectric, and an uninterrupted metallic feature over the liner a portion of the liner overlaying the gate dielectric, wherein the liner extends from a top surface of the uninterrupted metallic feature and covers sidewalls of the metallic feature, and wherein the gate dielectric, liner, and uninterrupted metallic feature collectively form a gate, a gate contact barrier, and a gate contact.
    Type: Grant
    Filed: February 9, 2015
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Systems and methods for fabricating semiconductor devices at different levels
    Patent number: 9331075
    Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: May 3, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Integrated circuit having a MOM capacitor and method of making same
    Patent number: 9318431
    Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • FinFET structure with different fin heights and method for forming the same
    Patent number: 9318367
    Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins protruding over a substrate, wherein two adjacent first fins are separated from each other by a plurality of first isolation regions and two adjacent second fins are separated from each other by a plurality of second isolation regions. The method further comprises applying a first ion implantation process to the first isolation region, wherein dopants with a first polarity type are implanted in the first isolation region, applying a second ion implantation process to the second isolation region, wherein dopants with a second polarity type are implanted in the second isolation region and recessing the first isolation regions and the second isolation regions through an etching process.
    Type: Grant
    Filed: February 27, 2013
    Date of Patent: April 19, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chi-Kang Liu, Chi-Wen Liu
  • Display screen portion with transitional progress bar graphical user interface
    Patent number: D755223
    Type: Grant
    Filed: January 16, 2014
    Date of Patent: May 3, 2016
    Assignee: VIVOTEK INC.
    Inventors: Chien-Wen Liu, Ting-Wen Chen, Tao-Cheng Yang