Abstract: An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Abstract: A biological particle analyzer is disclosed and includes a microchannel including an end coupled to a first drive electrode, another end coupled to a second drive electrode, a first detection area at an upstream location and an excitation area at a downstream location for containing particles flowing from the upstream location to the downstream location inside the microchannel, a first detection circuit coupled to the first detection area for outputting a first detection result when at least one particle has arrived at the first detection area, a light emission source, and a control module coupled to the first detection circuit and the light emission source for determining when to turn on or off the light emission source according to the first detection result.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: The present disclosure provides one embodiment of a method of forming a tunnel field effect transistor (TFET). The method includes forming a semiconductor mesa on a semiconductor substrate; performing a first implantation to the semiconductor substrate and the semiconductor mesa to form a drain of a first type conductivity; forming a first dielectric layer on the semiconductor substrate and sidewall of the semiconductor mesa; forming a gate stack on the sidewall of the semiconductor mesa and the first dielectric layer; forming a second dielectric layer on the first dielectric layer and the gate stack; and forming, on the semiconductor mesa, a source having a second type conductivity opposite to the first type conductivity. The gate stack includes a gate dielectric and a gate electrode on the gate dielectric. The source, drain and gate stack are configured to form the TFET.

Abstract: Electrostatic discharge protection circuits and methods for protecting a core circuit from an electrostatic discharge event. The protection circuit may include a first anti-parallel diode pair including a first terminal coupled to an input/output pad, and a second anti-parallel diode pair including a second terminal coupled to a negative power supply voltage. The second anti-parallel diode pair is coupled in series with the first anti-parallel diode pair at a node. An offset pad is coupled to the node. The offset pad is configured to receive a first signal that is a duplicate of a second signal that is received at the input/output pad.

Abstract: Methods for forming integrated circuit structures are provided. The method includes providing a substrate including a first diffusion region, a second diffusion region, and an isolation structure separating the first diffusion region and the second diffusion region. The method further includes forming a gate structure over the substrate and forming an inter-layer dielectric (ILD) layer over the substrate. The method further includes forming a cutting mask over a portion of the gate structure over the isolation structure, and the cutting mask has an extending portion covering a portion of the ILD layer. The method further includes forming a photoresist layer having an opening, and a portion of the extending portion of the cutting mask is exposed by the opening. The method further includes etching the ILD layer through the opening to form a trench and filling the trench with a conductive material to form a contact.

Abstract: A method for forming FinFETs comprises forming a plurality of first fins and a plurality of second fins over a substrate and embedded in isolation regions, depositing a first photoresist layer over the substrate, removing the first photoresist layer over an n-type region, applying a first ion implantation process to the first isolation regions, wherein dopants with a first polarity type are implanted in the first isolation regions, depositing a second photoresist layer over the substrate, removing the second photoresist layer over a p-type region, applying a second ion implantation process to the second isolation regions, wherein dopants with a second polarity type are implanted in the second isolation regions, applying an annealing process to the isolation regions and recessing the first isolation regions and the second isolation regions through an etching process.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a substrate; a nanowire structure protruding from the substrate comprising a channel region between a source region and a drain region; a pair of silicide regions extending into opposite sides of the source region, wherein each of the pair of silicide regions comprising a vertical portion adjacent to the source region and a horizontal portion adjacent to the substrate; and a metal gate surrounding a portion the channel region.

Abstract: A pattern based audio searching method includes labeling a plurality of source audio data based on patterns to obtain audio label sequences of the source audio data; obtaining, with a processing device, an audio label sequence of target audio data; determining matching degree between the target audio data and the source audio data according to a predetermined matching rule based on the audio label sequence of the target audio data and the audio label sequences of the source audio data; and outputting source audio data having matching degree higher than a predetermined matching threshold as a search result.

Abstract: A semiconductor package is disclosed, which includes: a carrier having at least an opening; a plurality of conductive traces formed on the carrier and in the opening; a first semiconductor element disposed in the opening and electrically connected to the conductive traces; a second semiconductor element disposed on the first semiconductor element in the opening; and a redistribution layer structure formed on the carrier and the second semiconductor element for electrically connecting the conductive traces and the second semiconductor element. Since the semiconductor elements are embedded and therefore positioned in the opening of the carrier, the present invention eliminates the need to perform a molding process before forming the redistribution layer structure and prevents the semiconductor elements from displacement.

Abstract: A representative method for fabricating a field effect transistor comprises forming a source region and a drain region disposed in a substrate; forming a gate structure over the substrate, the gate structure comprising sidewalls and a top surface, the gate structure interposing the source region and the drain region; forming a contact etch stop layer (CESL) over at least a portion of the top surface of the gate structure; forming an interlayer dielectric layer over the CESL; forming a gate contact extending through the interlayer dielectric layer; and forming a source contact and a drain contact extending through the interlayer dielectric layer, wherein a first distance between an edge of the source contact and a first corresponding edge of the CESL is about 1 nm to about 10 nm.

Abstract: The present disclosure relates to a method and an apparatus for backing up data, and an electronic device. The method includes: receiving backup data from a terminal; determining account information that the terminal has logged in to the electronic device; and storing the backup data to a path corresponding to the account information in the electronic device. By the technical solutions of the present disclosure, the backup data may be stored according to the account information, which helps to improve security and privacy of the backup data of each account, and facilitates router's management of backup data.

Abstract: A measurement device with electroencephalography (EEG) and electrocardiography (ECG) functionalities includes a shell and a turning structure. The shell includes a first contact and a second contact located at a first side of the shell; and a third contact. The turning structure, disposed on the shell, is utilized for adjusting the third contact to be located at the first side when the measurement device is in an EEG mode, and adjusting the third contact to be located at a second side of the shell when the measurement device is in an ECG mode, wherein the second side is substantially opposite to the first side.

Abstract: A precursor for labeling therapeutic agents for liver cancer and a method for manufacturing the same are revealed. The chemical structure of the precursor has a ligand linked to complex compounds of radioisotopes. Moreover, the chemical structure of the precursor further includes a specific functional group soluble in Lipiodol or having properties of Lipiodol. Thus the radioisotopes attached to the precursor are allowed to retain in hepatic tissues of patients with liver cancer for internal radiation therapy of liver cancer.

Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.

Abstract: An improved semiconductor device is provided whereby the semiconductor device is defined by a layered structure comprising a first dielectric layer, a data storage material disposed on the first dielectric layer, and a second dielectric layer disposed on the data storage material, the layered structured substantially forming the outer layer of the semiconductor device. For example, the semiconductor device may be a SONOS structure having an oxide-nitride-oxide (ONO) film that substantially surrounds the SONOS structure. The invention also provides methods for fabricating the semiconductor device and the SONOS structure of the invention.

Abstract: An embodiment includes a substrate, wherein a portion of the substrate extends upwards forming a fin, a gate dielectric over a top surface and at least portions of sidewalls of the fin, a gate electrode over the gate dielectric, and a contact over and extending into the gate electrode, wherein the contact has a first width above the gate electrode and a second width within the gate electrode, the first width being smaller than the second width.

Abstract: A fitness transmission apparatus including an information carrying assembly and an information reading assembly is provided. The information carrying assembly is disposed on a fitness equipment. The information carrying assembly is configured to record a weight information of the fitness equipment by using a plurality of information record combinations. The information reading assembly is disposed on the fitness equipment. The information reading assembly is configured to read the weight information in a predetermined manner based on types of the information record combinations. The information reading assembly is paired to the information carrying assembly in the predetermined manner to read the weight information. The information reading assembly transmits the read weight information to an electronic device. Furthermore, an information processing method is also provided.

Abstract: The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.

Abstract: A method of fabricating a semiconductor device comprises forming a fin structure extending from a substrate, the fin structure comprising a first fin, a second fin, and a third fin between the first fin and the second fin. The method further comprises forming germanide over a first facet of the first fin, a second facet of the second fin, and a substantially planar surface of the third fin, wherein the first facet forms a first acute angle with a major surface of the substrate and is substantially mirror symmetric with the second facet, and wherein the substantially planar surface of the third fin forms a second acute angle smaller than the first acute angle with the major surface of the substrate.