Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.

Abstract: A measurement device with electroencephalography (EEG) and electrocardiography (ECG) functionalities includes a shell and a turning structure. The shell includes a first contact and a second contact located at a first side of the shell; and a third contact. The turning structure, disposed on the shell, is utilized for adjusting the third contact to be located at the first side when the measurement device is in an EEG mode, and adjusting the third contact to be located at a second side of the shell when the measurement device his in an ECG mode, wherein the second side is substantially opposite to the first side.

Abstract: A measurement device with electroencephalography (EEG) and electrocardiography (ECG) functionalities includes a first shell having ECG functionality and a second shell. The first shell includes a first contact and a second contact located at a first side of the first shell; and a third contact located at a second side of the first shell, wherein the second side of the first shell is substantially opposite to the first side of the first shell. The second shell includes a fixing device, for connecting with and fixing on the first shell; and a fourth contact, a fifth contact and a sixth contact, located at a first side of the second shell, for electrically connecting with the first contact, the second contact and the third contact respectively when the first shell is connected to and fixed on the fixing device, in order to perform EEG measurement.

Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.

Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.

Abstract: Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.

Abstract: A method includes providing a first source/drain contact, providing a second source/drain contact, and surrounding the first and second source/drain contacts with a dielectric material layer. The providing a first source/drain contact and the providing a second source/drain contact are performed one after the other.

Abstract: The present disclosure relates to a transistor device having an epitaxial carbon layer and/or a carbon implantation region that provides for a low variation of voltage threshold, and an associated method of formation. In some embodiments, the transistor device has an epitaxial region arranged within a recess within a semiconductor substrate. The epitaxial region has a carbon doped silicon epitaxial layer and a silicon epitaxial layer disposed onto the carbon doped silicon epitaxial layer. A gate structure is arranged over the silicon epitaxial layer. The gate structure has a gate dielectric layer disposed onto the silicon epitaxial layer and a gate electrode layer disposed onto the gate dielectric layer. A source region and a drain region are arranged on opposing sides of a channel region disposed below the gate structure.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

Abstract: A method of manufacturing an interposer substrate, including providing a carrier having a first circuit layer formed thereon, forming a plurality of conductive pillars on the first circuit layer, forming a first insulating layer on the carrier, with the conductive pillars being exposed from the first insulating layer, forming on the conductive pillars a second circuit layer that is electrically connected to the conductive pillars, forming a second insulating layer on the second surface of the first insulating layer and the second circuit layer, exposing a portion of a surface of the second circuit layer from the second insulating layer, and removing the carrier. The invention further provides the interposer substrate as described above.

Abstract: The present invention provides for compounds of Formula I-I and embodiments and salts thereof for the treatment of diseases (e.g., neurodegenerative diseases). R1, R2, R3, X1, X2, A and Cy variable in Formula I-I all have the meaning as defined herein.

Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.

Abstract: Systems and methods are provided for fabricating semiconductor device structures on a substrate. For example, a substrate including a first region and a second region is provided. One or more first semiconductor device structures are formed on the first region. One or more semiconductor fins are formed on the second region. One or more second semiconductor device structures are formed on the semiconductor fins. A top surface of the semiconductor fins is higher than a top surface of the first semiconductor device structures.

Abstract: The present disclosure relates to a method and a device for backing up data. The method includes: determining whether a new file of a predetermined type exists locally; calculating a checked value corresponding to the new file according to a predetermined algorithm if the new file of the predetermined type exists; sending a query request containing the checked value to a connected router, so as to query whether a file having the checked value is stored in the router; and backing up the new file to the router if determining that no file having the checked value is stored in the router according to a query result returned from the router.

Abstract: A semiconductor device includes a nanowire structure and a stressor. The nanowire structure includes a first channel section and a second channel section. The stressor subjects the first channel section to a first strain level and the second channel section to a second strain level greater than the first strain level. The difference between the second strain level and the first strain level is less than the second strain level.

Abstract: A method controls the discharge of temperature-conditioned air from a plurality of zone outlets of an automotive HVAC system via an open architecture multi-zone HVAC unit having a single blower fan, an evaporator downstream of the blower and a heater downstream of the evaporator, wherein each zone in the module includes a temperature mix door for proportioning hot and cold air, which is controlled by a separate Discharge Temperature Maintenance control (DTM control), and an output valve for controlling a zonal output flow rate. The output valve of each zone outlet is placed in an output valve position associated with a target resistance; and the single blower fan is operated at a minimum voltage required for generating a total requested blower output flowrate.

Abstract: An embodiment is a bump bond pad structure that comprises a substrate comprising a top layer, a reinforcement pad disposed on the top layer, an intermediate layer above the top layer, an intermediate connection pad disposed on the intermediate layer, an outer layer above the intermediate layer, and an under bump metal (UBM) connected to the intermediate connection pad through an opening in the outer layer. Further embodiments may comprise a via mechanically coupling the intermediate connection pad to the reinforcement pad. The via may comprise a feature selected from the group consisting of a solid via, a substantially ring-shaped via, or a five by five array of vias. Yet, a further embodiment may comprise a secondary reinforcement pad, and a second via mechanically coupling the reinforcement pad to the secondary reinforcement pad.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a nanowire structure comprises a first semiconductor material having a first lattice constant and a first linear thermal expansion constant; and a second semiconductor material having a second lattice constant and a second linear thermal expansion constant surrounding the first semiconductor material, wherein a ratio of the first lattice constant to the second lattice constant is from 0.98 to 1.02, wherein a ratio of the first linear thermal expansion constant to the second linear thermal expansion constant is greater than 1.2 or less than 0.8.

Abstract: The invention relates to a high pressure water pump and a steam powered nailing gun having the high pressure water pump. In certain embodiments, high pressure water pump includes: an upper pump body, a lower pump body, a water discharge valve, a water intake valve, a plunger, a guide sleeve, a hammering cap, an adjustment knob, and an evacuation valve. Both upper and lower pump body are connected by connecting bolts. A sealing ring is disposed between upper and lower pump body and a sealing element is disposed between the upper pump body and plunger. Plunger is sheathed in upper pump body. The hammering cap is threadedly connected to the plunger. The adjustment knob is connected to an upper end of upper pump body. The hammering cap is moveably connected to the adjustment knob through the plunger. A plunger reset spring is disposed between hammering cap and adjustment knob.

Abstract: The invention relates to a cylinder cover for a cylinder of a piston mechanism. In certain embodiments, the cylinder cover includes a cylinder cover body, a valve plate, and a one-directional valve. The cylinder cover body has an exhaust port, and an oil intake. The exhaust port and oil intake are disposed on outer circumference of the cylinder cover body. The one directional oil valve is formed by a compression spring and a ball. An inner end of the oil intake is connected to the compression spring through the ball and the ball is disposed between one end of the compression spring and the inner end of the oil intake. The valve plate is retained on an inner wall of the cylinder cover body by a retaining nut. The cylinder cover further has an auxiliary heating rod inside cylinder cover body for pre-heating cylinder cover to a predetermined temperature.