Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.

Abstract: Disclosed is a method for fabricating a semiconductor package, including providing a package unit having an insulating layer and at least a semiconductor element embedded into the insulating layer, wherein the semiconductor element is exposed from the insulting layer and a plurality of recessed portions formed in the insulating layer; and electrically connecting a redistribution structure to the semiconductor element. The formation of the recessed portions release the stress of the insulating layer and prevent warpage of the insulating layer from taking place.

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract: A method for managing virtual control interface of an electronic device, and an associated apparatus and an associated computer program product are provided, where the method includes: utilizing a specific set of common user interfaces (UIs) as a common service for a plurality of applications, wherein the specific set of common UIs is a set of virtual control interfaces to be displayed on a screen, and the specific set of common UIs is provided by a system framework running on the electronic device, rather than being provided by any of the plurality of applications; and displaying the specific set of common UIs to allow a user to control the electronic device through the specific set of common UIs. The method may further include: selecting the specific set of common UIs from a plurality of sets of common UIs.

Abstract: A fin structure of a semiconductor device, such as a fin field effect transistor (FinFET), and a method of manufacture, is provided. In an embodiment, trenches are formed in a substrate, and a liner is formed along sidewalls of the trenches, wherein a region between adjacent trenches define a fin. A dielectric material is formed in the trenches. Portions of the semiconductor material of the fin are replaced with a second semiconductor material and a third semiconductor material, the second semiconductor material having a different lattice constant than the substrate and the third semiconductor material having a different lattice constant than the second semiconductor material. Portions of the second semiconductor material are oxidized.

Abstract: A semiconductor device includes a substrate, a first source/drain (S/D), a second S/D, and a semiconductor sheet unit. The substrate extends in a substantially horizontal direction. The first S/D is formed on the substrate. The second S/D is disposed above the first S/D. The semiconductor sheet unit extends in a substantially vertical direction and interconnects the first S/D and the second S/D. A method for fabricating the semiconductor device is also disclosed.

Abstract: A near field antenna adapted to an object detecting device, for sensing a plurality of units under test of at least an object under test. The near field antenna comprises a periodic guided-wave structure, a metallic reflection portion and at least two near field magnetic coupling antennas. The periodic guided-wave structure disposed below the object under test has a plurality of conductive units periodically arranged on a first plane. The metallic reflection portion is disposed under the periodic guided-wave structure to form an enclosed space. The near field magnetic coupling antennas are disposed on a second plane parallel to the periodic guided-wave structure, and are located in the enclosed space. The feed point and the ground point of each near field magnetic coupling antenna are fed by a coaxial cable with a feeding direction parallel to the periodically arranged conductive units.

Abstract: A fixed-line trimmer head for a rotary trimmer device includes the upper portion having a periphery, wherein the upper portion has a plurality of openings spaced from the periphery; and a plurality of mechanisms. Each mechanism can hold a strip of line and includes a post portion disposed through one of the openings in the upper portion, and a flange disposed at one end of the post portion and sandwiched between the upper portion and lower portion of the trimmer head to prevent vertical movement of the mechanism. The post portion includes two line channels, each line channel defining a passageway to receive the same strip of line, wherein at least one of the line channels is curved such that any portion of the strip of line being received through the passageway of that line channel is bent at that portion of the strip of line away from the second line channel while passing through that at least one line channel that is curved.

Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first semiconductor mesa formed on the semiconductor substrate within the first region; a second semiconductor mesa formed on the semiconductor substrate within the second region; and a field effect transistor (FET) formed on the semiconductor substrate. The FET includes a first doped feature of a first conductivity type formed in a top portion of the first semiconductor mesa; a second doped feature of a second conductivity type formed in a bottom portion of the first semiconductor mesa, the second semiconductor mesa, and a portion of the semiconductor substrate between the first and second semiconductor mesas; a channel in a middle portion of the first semiconductor mesa and interposed between the source and drain; and a gate formed on sidewall of the first semiconductor mesa.

Abstract: Systems and methods are provided for generating a semiconductor device on a single semiconductor substrate. A single semiconductor substrate is generated that includes a Silicon material portion and a Germanium material portion. A first set of source/drain contacts is formed from a first metal on the Silicon material portion. The first set of source/drain contacts is annealed with the Silicon material portion at a first temperature. A second set of source/drain contacts is formed from a second metal on the Germanium material portion after heating the semiconductor substrate to the first temperature, and the second set of source/drain contacts is annealed with the Germanium material portion at a second temperature, where the second temperature is less than the first temperature.

Abstract: In one embodiment, a method includes providing a semiconductor substrate having a trench disposed thereon and forming a plurality of layers in the trench. The plurality of layers formed in the trench is etched thereby providing at least one etched layer having a top surface that lies below a top surface of the trench. In a further embodiment, this may provide for a substantially v-shaped opening or entry to the trench for the formation of further layers.

Abstract: A portable electronic apparatus assembly includes a tabular electronic device and a supporting device. The supporting device includes a base, a connecting member pivotally connected to the base, and a supporting member pivotally connected to the connecting member. The connecting member can rotate about a first rotation axis relative to the base. The supporting member can rotate about a second rotation axis relative to the connecting member. The first rotation axis and the second rotation axis are nonparallel. The supporting device can support the tabular electronic device by accommodating the tabular electronic device in an accommodating slot of the supporting member. Thereby, unfolding and folding of the supporting member relative to the base is more flexible. The whole thickness of the supporting device after folded can avoid being restrained by the thickness of the tabular electronic device.

Abstract: HVAC unit has a single blower fan, an evaporator downstream of the blower and a heater downstream of the evaporator, wherein each zone outlet includes a temperature mixing door for controlling portions of hot and cold air and an output valve for controlling a zonal output flow rate. A method is devised to control the discharge of temperature-conditioned air from a plurality of zone outlets of an automotive HVAC system via such an HVAC unit by the steps of reading an operator-requested zonal discharge blower level for each of the zone outlets; converting each zonal discharge blower level request to a zonal flowrate request; calculating a total requested output flowrate as a summation of all zonal flowrate requests; and adjusting a blower voltage to a minimum voltage required for generating the total requested output flowrate.

Abstract: A fin structure suitable for a FinFET and having a buried insulator layer is disclosed. In an exemplary embodiment, a semiconductor device comprises a substrate with a first semiconductor material and having a fin structure formed thereupon. The fin structure includes a lower region proximate to the substrate, a second semiconductor material disposed on the lower region, a third semiconductor material disposed on the second semiconductor material, and an insulating material selectively disposed on the second semiconductor material such that the insulating material electrically isolates a channel region of the fin structure and further such that the insulating material exerts a strain on the channel region. The semiconductor device further comprises an isolation feature disposed adjacent to the fin structure.

Abstract: Systems and methods for frequency offset estimation are provided. A channel impulse response and multi-user signal parameter are jointly estimated. Based on the multi-user signal parameter, a determination is made as to whether the signal contains a single-user signal or a multi-user signal. Then, frequency offset estimation is performed based on this determination. For example, noiseless sample estimates are generated depending on whether the signal is a single-user signal or a multi-user signal.

Abstract: A semiconductor device with variable channel strain is provided. The semiconductor device comprises a nanowire structure formed as a channel between a source region and a drain region. The nanowire structure has a first channel section subjected to a first strain level and joined with a second channel section subjected to a second strain level different from the first strain level. The first channel section is coupled adjacent to the drain region and the second channel section is coupled adjacent to the source region. The semiconductor device further comprises a gate region that has a first strain section and a second strain section. The first strain section is configured to cause the first channel section to be subjected to the first strain level and the second strain section is configured to cause the second channel section to be subjected to the second strain level.

Abstract: A semiconductor arrangement and method of formation are provided herein. A semiconductor arrangement includes a metal connect in contact with a first active region and a second active region, and over a shallow trench isolation region located between the first active region and a second active region. A method of forming the semiconductor arrangement includes recessing the metal connect over the STI region to form a recessed portion of the metal connect. Forming the recessed portion of the metal connect in contact with the first active region and the second active region mitigates RC coupling, such that a first gate is formed closer to a second gate, thus reducing a size of a chip on which the recessed portion is located.

Abstract: A near field antenna adapted to an object detecting device, for sensing a plurality of units under test of at least an object under test. The near field antenna comprises a periodic guided-wave structure, a metallic reflection portion and at least two near field magnetic coupling antennas. The periodic guided-wave structure disposed below the object under test has a plurality of conductive units periodically arranged on a first plane. The metallic reflection portion is disposed under the periodic guided-wave structure to form an enclosed space. The near field magnetic coupling antennas are disposed on a second plane parallel to the periodic guided-wave structure, and are located in the enclosed space. The feed point and the ground point of each near field magnetic coupling antenna are fed by a coaxial cable with a feeding direction parallel to the periodically arranged conductive units.

Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.

Abstract: A precursor for labeling therapeutic agents for liver cancer and a method for manufacturing the same are revealed. The chemical structure of the precursor has a ligand linked to complex compounds of radioisotopes. Moreover, the chemical structure of the precursor further includes a specific functional group soluble in Lipiodol or having properties of Lipiodol. Thus the radioisotopes attached to the precursor are allowed to retain in hepatic tissues of patients with liver cancer for internal radiation therapy of liver cancer.