Abstract: A substrate structure includes a dielectric layer, a first circuit layer, a second circuit layer and at least one conductive pillar. The dielectric layer has a first surface and a second surface opposite to the first surface. The first circuit layer is disposed adjacent to the first surface of the dielectric layer. The second circuit layer is disposed adjacent to the second surface of the dielectric layer and electrically connected to the first circuit layer. The second circuit layer includes a plurality of pads and at least one trace disposed between two adjacent pads of the plurality of pads. The at least one conductive pillar is tapered toward the second circuit layer and disposed on one of the pads. A portion of the second surface of the dielectric layer is exposed from the second surface layer.

Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.

Abstract: A semiconductor package device includes an interconnection structure, an electronic component, a package body and an electrical contact. The dielectric layer has a top surface and a bottom surface. The dielectric layer defines a cavity extending from the bottom surface into the dielectric layer. A patterned conductive layer is disposed on the top surface of the dielectric layer. The conductive pad is at least partially disposed within the cavity and electrically connected to the patterned conductive layer. The conductive pad includes a first metal layer and a second metal layer. The second metal layer is disposed on the first metal layer and extends along a lateral surface of the first metal layer. The electronic component is electrically connected to the patterned conductive layer. The package body covers the electronic component and the patterned conductive layer. The electrical contact is electrically connected to the conductive pad.

Abstract: A novel magnetic switch, comprising a housing, a terminal A and a terminal B, wherein an inner cavity of the housing is internally provided with a magnetic body and a tongue plate, one end of the tongue plate is movably connected to the upper end of the terminal B, the magnetic body, which is integrally linked to the tongue plate, is capable of being raised thereon; the other end of the tongue plate is disposed above the terminal A; the upper end of the terminal A is provided with an arc-removing apparatus, the arc-removing apparatus is provided with a stationary contact, and the other end of the tongue plate is provided with a movable contact. The magnetic switch has an effective structure, thus improving the work stability and prolonging the service life of the switch.

Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

Abstract: A semiconductor package device comprises an electronic component, a conductive bump and a first conductive layer. The electronic component has a top surface. The conductive bump is disposed on the top surface of the electronic component. The conductive bump includes a main body and a protruding portion. The first conductive layer covers a portion of the protruding portion. The first conductive layer has a first upper surface and a second upper surface. The first upper surface and the second upper surface are not coplanar.

Abstract: A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.

Abstract: A semiconductor package device comprises a first dielectric layer, a first conductive pad and a first conductive element. The first dielectric layer has a first surface and a second surface opposite to the first surface. The first dielectric layer defines a first opening tapered from the first surface toward the second surface. The first conductive pad is within the first opening and adjacent to the second surface of the first dielectric layer. At least a portion of the first conductive element is within the first opening. The first conductive element is engaged with (e.g., abuts) a sidewall of the first opening, the first conductive element having a first surface facing toward the first conductive pad, wherein the first surface of the first conductive element is spaced apart from the first conductive pad.

Abstract: A semiconductor package includes a substrate, a dielectric layer, at least one conductive pillar and an electrical device. The dielectric layer is disposed on the substrate and defines at least one through hole corresponding to the respective first pad of the substrate. The conductive pillar is disposed in the respective through hole. The conductive pillar includes a body portion and a cap portion. The body portion is physically connected to the cap portion, and the cap portion is electrically connected to the first pad. A maximum width of the cap portion is greater than a maximum width of the body portion. The electrical device is disposed on the dielectric layer and electrically connected to the body portion of the conductive pillar.

Abstract: A semiconductor package device includes a circuit layer having a top surface, a first electronic component disposed on the top surface of the circuit layer, and a first conductive element disposed on the top surface of the circuit layer, the first conductive element having a top surface. The first electronic component has an active surface and a back surface facing the top surface of the circuit layer. A distance between the active surface of the first electronic component and the top surface of the circuit layer is greater than a distance between the top surface of the first conductive element and the top surface of the circuit layer.

Abstract: A semiconductor package device comprises a passivation layer, a conductive element, a redistribution layer (RDL) and an electronic component. The passivation layer has a first surface and second surface opposite to the first surface. The conductive element is within the passivation layer. The conductive element defines a recess facing the second surface of the passivation layer. The RDL is on the passivation layer and electrically connected with the conductive element. The electronic component is disposed on the RDL and electrically connected with the RDL.

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: A semiconductor package device includes a carrier, a first electronic component, and a conductive element on the carrier. The first electronic component is over the carrier. The conductive element is on the carrier and electrically connects the first electronic component to the carrier. The conductive element includes at least one conductive particle and a solder material covering the conductive particle, and the conductive particle includes a metal core, a barrier layer covering the metal core, and a metal layer covering the barrier layer.

Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

Abstract: A via structure includes a base material, a first dielectric layer and a second dielectric layer. The base material includes a first surface and a second surface opposite to the first surface, and defines at least one through hole. The first dielectric layer is disposed on the first surface of the base material and includes a gradient surface exposed in the through hole of the base material. The second dielectric layer is disposed on the gradient surface of first dielectric layer.

Abstract: A method for operating an electronic device, and an electronic device, are provided. In the normal operation state of the electronic device, data which is stored in the main storage device of the electronic device is encrypted by a first encryption algorithm prior to being stored in a non-volatile storage device of the electronic device. The method includes the steps of generating snapshot data in the main storage device when the electronic device is entering a hibernation state, allocating space in the non-volatile storage device for storing the snapshot data, and storing the snapshot data in the space without encrypting the snapshot data using the first encryption algorithm.

Abstract: A semiconductor device includes at least one base element, at least one passivation layer, at least one circuit layer and at least one light absorbing layer. The base element includes at least one conductive pad. The passivation layer is disposed on the base element. The circuit layer is electrically connected to the conductive pad and disposed in the passivation layer. The light absorbing layer is disposed on the circuit layer.

Abstract: A memory access module for performing memory access management of a storage device includes a plurality of storage cells. Each storage cell has a number of possible bit(s) directly corresponding to possible states of the storage cell. The memory access module further includes: a read only memory for storing a program code; and a microprocessor, coupled to the read only memory, for executing the program code to perform the following steps: performing a plurality of sensing operations, wherein a first sensing operation corresponds to a first sensing voltage, and each subsequent sensing operation corresponds to a sensing voltage determined according to a result of the previous sensing operation; using the plurality of sensing operations to generate a first digital value and a second digital value of a storage cell; using the first and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: The present invention relates to an air-ground heterogeneous robot system path planning method based on a neighborhood constraint. A smallest heterogeneous robot system is formed by a ground mobile robot and an air flying robot. The steps of the method include the ground mobile robot and the air flying robot start from a start point at the same time, successively access N sub-task points for executing sub-tasks and finally reach a destination together. In the present invention, it is considered that the position of each sub-task point is allowed to be effective in a certain neighborhood, and a neighborhood constraint is introduced. In addition, the maximum speed constraints are considered respectively for the air flying robot and the ground mobile robot.

Abstract: A semiconductor package structure includes a first dielectric layer, a conductive element, a first circuit structure, a semiconductor die and an encapsulant. The first dielectric layer defines at least one through hole. The conductive element is disposed in the through hole and including a first portion and a second portion. A first surface of the first portion is substantially coplanar with a first surface of the first dielectric layer, and a portion of a first surface of the second portion is recessed from the first surface of the first dielectric layer. The first circuit structure is disposed on the first dielectric layer. The semiconductor die is electrically connected to the first circuit structure. The encapsulant covers the semiconductor die.