Abstract: A lamp includes a casing, an elastic cover and a main body. The casing has an opening. The elastic cover covers the casing. The main body is disposed at the casing, and includes a base plate, a rotating element, a moving element, a linking-up element and a force member. The rotating element is pivoted to the base plate and located at the opening. The moving element is disposed at the base plate. Two ends of the linking-up element are connected to the rotating element and the moving element, respectively. The force member is connected to the moving element. When the force member receives a force, the moving element is moved from a first position to a second position, the linking-up element brings the rotating element to rotate away the base plate, and the rotating element is protruded from the opening, and pushes against the elastic cover.

Abstract: A method for performing memory access includes: performing a first sensing operation corresponding to a first sensing voltage and performing at least a second sensing operation corresponding to a second sensing voltage to respectively generate a first digital value of a Flash cell of a Flash memory and a second digital value of the Flash cell of the Flash memory; using the first digital value, the second digital value, and charge distribution statistics information of the Flash memory to obtain soft information of a bit stored in the Flash cell, wherein the soft information corresponds to a threshold voltage of the Flash cell; and using the soft information to perform soft decoding.

Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.

Abstract: A semiconductor package device includes an interconnection structure, an electronic component, a package body and an electrical contact. The dielectric layer has a top surface and a bottom surface. The dielectric layer defines a cavity extending from the bottom surface into the dielectric layer. A patterned conductive layer is disposed on the top surface of the dielectric layer. The conductive pad is at least partially disposed within the cavity and electrically connected to the patterned conductive layer. The conductive pad includes a first metal layer and a second metal layer. The second metal layer is disposed on the first metal layer and extends along a lateral surface of the first metal layer. The electronic component is electrically connected to the patterned conductive layer. The package body covers the electronic component and the patterned conductive layer. The electrical contact is electrically connected to the conductive pad.

Abstract: A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.

Abstract: A semiconductor package structure includes a first semiconductor die, a second semiconductor die, a plurality of conductive elements, a first encapsulant and a second encapsulant. The second semiconductor die is disposed on the first semiconductor die. The conductive elements each comprises a first portion and a second portion and are disposed around the first semiconductor die and the second semiconductor die. The first encapsulant surrounds the first semiconductor die and the respective first portions of the conductive elements. The second encapsulant covers a portion of a top portion of the first semiconductor die and surrounds the respective second portions of the conductive elements.

Abstract: A semiconductor package device is provided that includes a first circuit layer having a first conductive layer and a first stud bump and a second circuit layer having a second conductive layer and a second stud bump. The first stud bump has a first portion and a second portion, and the second portion of the first stud bump is electrically connected to the second conductive layer. The second stud bump has a first portion and a second portion, and the second portion of the second stud bump is electrically connected to the first conductive layer. The first stud bump partially overlaps the second stud bump in a direction substantially perpendicular to the first circuit layer.

Abstract: A semiconductor device package includes a circuit layer, an electronic component, an electronic component, a first passivation layer and a second passivation layer. The circuit layer has a first surface. The electronic component is disposed on the first surface of the circuit layer. The first passivation layer is disposed on the first surface of the circuit layer. The first passivation layer has a first surface facing away the circuit layer. The second passivation layer is disposed on the first surface of the first passivation layer. The second passivation layer has a second surface facing away the circuit layer. A uniformity of the first surface of the first passivation layer is greater than a uniformity of the second surface of the second passivation layer.

Abstract: A semiconductor substrate includes a dielectric layer, a first conductive layer, a first barrier layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The first conductive layer is disposed adjacent to the first surface of the dielectric layer. The first barrier layer is disposed on the first conductive layer. The conductive post is disposed on the first barrier layer. A width of the conductive post is equal to or less than a width of the first barrier layer.

Abstract: A Flash memory access module performs memory access management of a Flash storage device including a plurality of storage cells. The Flash memory access module includes: a read only memory for storing a program code; and a microprocessor which executes the program code to perform the following steps: performing a first sensing operation corresponding to a first sensing voltage in a storage cell, and performing a second sensing operation in the storage cell; using the first sensing operation and at least the second sensing operation to generate a first digital value and a second digital value, respectively, of the storage cell; using the first digital value and the second digital value to obtain soft information of a same bit stored in the storage cell; and using the soft information to perform soft decoding.

Abstract: An electronic device includes a first substrate, a first conductor, a first insulation layer, a second substrate, a second conductor, a second insulation layer. The first substrate has a first surface. The first conductor is disposed on the first surface of the first substrate. The first insulation layer is on the first conductor. The second substrate has a second surface facing toward the first surface of the first substrate. The second conductor is disposed on the second surface of the second substrate. The second insulation layer is on the second conductor. The first insulation layer is in contact with a sidewall of the second conductor. The second insulation layer is in contact with a sidewall of the first conductor. A coefficient of thermal expansion (CTE) of the first insulation layer is greater than a CTE of the first conductor.

Abstract: A connection structure is provided. The connection structure includes an intermediate conductive layer, a first conductive layer and a second conductive layer. The intermediate conductive layer includes a first surface and a second surface opposite to the first surface. The intermediate conductive layer has a first coefficient of thermal expansion. The first conductive layer is in contact with the first surface of the intermediate conductive layer. The first conductive layer has a second CTE. The second conductive layer is in contact with the second surface of the intermediate conductive layer. The first conductive layer and the second conductive layer are formed of the same material. One of the first CTE and the second CTE is negative, and the other is positive.

Abstract: An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.

Abstract: Methods, apparatuses, and systems for substrate processing for lowering contact resistance in at least contact pads of a semiconductor device are provided herein. In some embodiments, a method of substrate processing for lowering contact resistance of contact pads includes: circulating a cooling fluid in at least one channel of a pedestal; and exposing a backside of the substrate located on the pedestal to a cooling gas to cool a substrate located on the pedestal to a temperature of less than 70 degrees Celsius. In some embodiments in accordance with the present principles, the method can further include distributing a hydrogen gas or hydrogen gas combination over the substrate.

Abstract: The present invention relates to an air-ground heterogeneous robot system path planning method based on a neighborhood constraint. A smallest heterogeneous robot system is formed by a ground mobile robot and an air flying robot. The steps of the method include the ground mobile robot and the air flying robot start from a start point at the same time, successively access N sub-task points for executing sub-tasks and finally reach a destination together. In the present invention, it is considered that the position of each sub-task point is allowed to be effective in a certain neighborhood, and a neighborhood constraint is introduced. In addition, the maximum speed constraints are considered respectively for the air flying robot and the ground mobile robot.

Abstract: A semiconductor package includes a dielectric layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive post is disposed in the dielectric layer. The conductive post includes a first portion and a second portion disposed above the first portion. The second portion of the conductive post is recessed from the second surface of the dielectric layer.

Abstract: A capacitor structure is disclosed. The capacitor structure includes a substrate, and a first electrode disposed on the substrate, the first electrode including a conductive layer, a first conductive post electrically connected to the conductive layer and a second conductive post electrically connected to the conductive layer. The capacitor structure further includes a planarization layer disposed on and covering the first electrode, the planarization layer disposed in a space between the first conductive post and the second conductive post, a first dielectric layer disposed on the planarization layer and in the space between the first conductive post and the second conductive post, and a second electrode disposed on the first dielectric layer.

Abstract: A semiconductor substrate includes a first dielectric structure and a first circuit layer. The first circuit layer is embedded in the first dielectric structure. The first circuit layer does not protrude from a first surface of the first dielectric structure. The first circuit layer includes at least one conductive segment. The conductive segment includes a first portion adjacent to the first surface of the first dielectric structure and a second portion opposite to the first portion. A width of the first portion of the conductive segment is different from a width of the second portion of the conductive segment.

Abstract: A semiconductor device package includes a first dielectric layer, a first conductive layer, an electronic component, a second dielectric layer, a second conductive layer and a package body. The first dielectric layer has a top surface, a bottom surface opposite to the top surface and a lateral surface extending between the top surface and the bottom surface. The first conductive layer is disposed on the top surface of the first dielectric layer. The electronic component is disposed on the top surface of the first dielectric layer. The second dielectric layer covers the bottom surface and a first portion of the lateral surface of the first dielectric layer and exposes a second portion of the lateral surface of the first dielectric layer. The second conductive layer is disposed on a bottom surface of the second dielectric layer and electrically connected to the first conductive layer.

Abstract: A semiconductor package includes a dielectric layer and a conductive post. The dielectric layer has a first surface and a second surface opposite to the first surface. The conductive post is disposed in the dielectric layer. The conductive post includes a first portion and a second portion disposed above the first portion. The second portion of the conductive post is recessed from the second surface of the dielectric layer.