Abstract: A semiconductor trace structure is provided for carrying a heat source. The semiconductor device package includes a dielectric structure having a first surface configured to receive the heat source and a second surface opposite to the first surface; a cavity defined by the dielectric structure to accommodate a fluid. The cavity includes a first passage portion between the first surface and the second surface. A first area of the first passage portion is closer to the heat source than a second area of the first passage portion, and that the first area is greater than the second area from a top view perspective. A method for manufacturing the semiconductor trace structure is also provided.

Abstract: At least some embodiments of the present disclosure relate to a semiconductor device package. The semiconductor device package comprises a carrier, a first patterned conductive layer, an interconnection structure, a first semiconductor device, an encapsulant, a second patterned conductive layer, and a passivation layer. The carrier has a first surface and a second surface opposite to the first surface. The first patterned conductive layer is adjacent to the first surface of the carrier. The interconnection structure is disposed on the first patterned conductive layer and electrically connected to the first patterned conductive layer. The first semiconductor device is disposed on the interconnection structure and electrically connected to the interconnection structure. The encapsulant is disposed on the first patterned conductive layer and encapsulates the semiconductor device and the interconnection structure.

Abstract: A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.

Abstract: A semiconductor device package includes an interposer and a semiconductor device. The interposer has a sidewall defining a space. The semiconductor device is disposed within the space and in contact with the sidewall. An interposer includes a first surface, a second surface and a third surface. The first surface has a first crystal orientation. The second surface is opposite the first surface and has the first crystal orientation. The third surface connects the first surface to the second surface, and defines a space. An angle defined by the third surface and the first surface ranges from about 90° to about 120°.

Abstract: A semiconductor device package includes an electronic component, a first set of conductive wires electrically connected to the electronic component, and an insulation layer surrounding the first set of conductive wires. The insulation layer exposes a portion of the first set of the conductive wires. The insulation layer is devoid of a filler.

Abstract: A semiconductor device package includes an electronic component, a first substrate, a first bonding wire and a second substrate. The electronic component has a first surface. The first substrate is disposed on the first surface of the electronic component. The first bonding wire electrically connects the first substrate to the electronic component. The second substrate is disposed on the first surface of the electronic component. The second substrate defines an opening accommodating the first substrate and the first bonding wire.

Abstract: An electrical device includes a substrate and a via. The substrate has a first surface and defines a recess in the first surface. The via is disposed in the recess. The via includes an insulation layer, a first conductive layer and a second conductive layer. The insulation layer is disposed on the first surface of the substrate and extends at least to a sidewall of the recess. The first conductive layer is disposed adjacent to the insulation layer and extends over at least a portion of the first surface. The second conductive layer is disposed adjacent to the first conductive layer and extends over at least a portion of the first surface. The second conductive layer has a negative coefficient of thermal expansion (CTE).

Abstract: A semiconductor device package includes a dielectric layer, a first conductive pattern and a first semiconductor device. The dielectric layer has a first surface, wherein a surface uniformity of the first surface is substantially equal to or less than 5%. The first conductive pattern is disposed on the first surface of the dielectric layer, wherein the first conductive pattern includes a first conductive trace, and a line width of the first conductive trace substantially ranges from about 0.5 ?m and about 2 ?m. The first semiconductor device is disposed on the first surface of the dielectric layer and electrically connected to the first conductive pattern.

Abstract: Various embodiments relate to a semiconductor package structure. The semiconductor package structure includes a first chip having a first surface and a second surface opposite the first surface. The semiconductor package structure further includes a supporter surrounding an edge of the first chip, and the supporter includes a recessed portion. The semiconductor package structure further includes a conductive layer disposed over the first surface of the first chip and electrically connected to the first chip. The semiconductor package structure further includes an insulation layer disposed over the first surface of the first chip. The semiconductor package structure further includes an encapsulant between the first chip and the supporter and surrounding at least the edge of the first chip.

Abstract: A semiconductor packaging device includes a first patterned insulation layer, a patterned conductive layer, a semiconductor device and an encapsulant. The first patterned insulation layer has a first surface, a second surface opposite the first surface, and an island portion having the first surface. The first patterned insulation layer defines a tapered groove surrounding the island portion. The patterned conductive layer is disposed on the first surface of the island portion. The semiconductor device electrically connects to the patterned conductive layer. The encapsulant encapsulates the semiconductor device, the first patterned insulation layer and the patterned conductive layer.

Abstract: A semiconductor device package includes a dielectric layer, a first conductive pattern and a first semiconductor device. The dielectric layer has a first surface, wherein a surface uniformity of the first surface is substantially equal to or less than 5%. The first conductive pattern is disposed on the first surface of the dielectric layer, wherein the first conductive pattern includes a first conductive trace, and a line width of the first conductive trace substantially ranges from about 0.5 ?m and about 2 ?m. The first semiconductor device is disposed on the first surface of the dielectric layer and electrically connected to the first conductive pattern.

Abstract: A semiconductor package device includes a first conductive structure, a second conductive structure and a dielectric layer. The first conductive structure has a tapered portion. The second conductive structure surrounds the tapered portion of the first conductive structure and is in direct contact with a side wall of the tapered portion of the first conductive structure. The dielectric layer surrounds the tapered portion of the first conductive structure and is in direct contact with the side wall of the tapered portion of the first conductive structure.

Abstract: A semiconductor package device comprises an electronic component, a conductive bump and a first conductive layer. The electronic component has a top surface. The conductive bump is disposed on the top surface of the electronic component. The conductive bump includes a main body and a protruding portion. The first conductive layer covers a portion of the protruding portion. The first conductive layer has a first upper surface and a second upper surface. The first upper surface and the second upper surface are not coplanar.

Abstract: An electronic device includes a first dielectric layer, a second dielectric layer and at least one first stud bump. The second dielectric layer is disposed on the first dielectric layer. The first stud bump is disposed in the first dielectric layer and the second dielectric layer. The first stud bump includes a bump portion and a stud portion, and the stud portion is disposed on the bump portion.

Abstract: A parking management system and a parking space management method are provided. In this system, intelligent parking locks are capable of performing two-way data communication with a cloud platform and executing an action instruction issued by the cloud platform, which realizes parking space sharing, open and intelligent management and monitoring. One-key navigation parking and one-key car searching can be realized since the intelligent parking locks include Bluetooth positioning and/or multiple GPS combined with mobile internet applications. The problems in searching for a parking space and searching for one's own car are hence well solved. The induction type parking locks control system ensures automatic locking and unlocking operations according to the distance between the mobile terminal and the parking locks, which significantly improves user's experiences.

Abstract: A substrate panel structure includes a plurality of sub-panels and a dielectric portion. Each of the sub-panels includes a plurality of substrate units. The dielectric portion is disposed between the sub-panels.

Abstract: An overcurrent protection method is provided. The overcurrent protection method is applied to a USB with a PD function. The overcurrent protection method includes the steps of converting an input voltage into a first voltage to provide power to the first electronic device; determining whether the working current of the first electronic device is greater than a first default value; determining whether the working current of the first electronic device is greater than a second default value; in response to the working current being greater than the first default value, a first sensing signal is generated to disable a switch and to form an open circuit between the first electronic device and the second electronic device; and in response to the working current being greater than the second default value, conversion of the input voltage into the first voltage is stopped.

Abstract: A semiconductor device package includes an interposer and a semiconductor device. The interposer has a sidewall defining a space. The semiconductor device is disposed within the space and in contact with the sidewall. An interposer includes a first surface, a second surface and a third surface. The first surface has a first crystal orientation. The second surface is opposite the first surface and has the first crystal orientation. The third surface connects the first surface to the second surface, and defines a space. An angle defined by the third surface and the first surface ranges from about 90° to about 120°.

Abstract: An optical device package includes a semiconductor substrate, and an optical device. The semiconductor substrate has a first surface, a second surface different in elevation from the first surface, and a profile connecting the first surface to the second surface. A surface roughness of the profile is greater than a surface roughness of the second surface. The optical device is disposed on the second surface and surrounded by the profile.

Abstract: A package device includes a circuit layer, at least one conductive segment, an encapsulant and a redistribution layer. The conductive segment is disposed on the circuit layer and has a first surface and a second surface. The encapsulant encapsulates at least a portion of the conductive segment and has a first upper surface. A first portion of the first surface and at least a portion of the second surface of the conductive segment are disposed above the first upper surface of the encapsulant. The redistribution layer is disposed on the encapsulant, the first portion of the first surface of the conductive segment, and the second surface of the conductive segment.