Patents by Inventor Wen Lu
Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240347909Abstract: The present disclosure provides an antenna package structure, including a first antenna and a first frequency selective surface structure. The first frequency selective surface structure is disposed above the first antenna, and includes a plurality of first patterns and a plurality of second patterns geometrically distinct from the plurality of the first patterns. The plurality of first patterns and the plurality of second patterns are configured to enhance gain and directivity of the first antenna.Type: ApplicationFiled: April 13, 2023Publication date: October 17, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
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Patent number: 12107151Abstract: A semiconductor device includes a gate structure on a substrate, a first spacer on sidewalls of gate structure, a second spacer on sidewalls of the first spacer, a polymer block adjacent to the first spacer and on a corner between the gate structure and the substrate, an interfacial layer under the polymer block, and a source/drain region adjacent to two sides of the first spacer. Preferably, the polymer block is surrounded by the first spacer, the interfacial layer, and the second spacer.Type: GrantFiled: June 13, 2023Date of Patent: October 1, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Fu-Jung Chuang, Tsuo-Wen Lu, Chia-Ming Kuo, Po-Jen Chuang, Chi-Mao Hsu
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Patent number: 12100624Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.Type: GrantFiled: February 15, 2022Date of Patent: September 24, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Ta-Wei Chiu, Ping-Hung Chiang, Chia-Wen Lu, Chia-Ling Wang, Wei-Lun Huang
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Patent number: 12095187Abstract: A receptacle connector with a metal housing encircling an insulative housing with a slot to receive a paddle card of a plug connector. The metal housing may have a tab engaging a wall of the insulative housing bounding the slot. The tab may be positioned such that, if a plug is improperly inserted into the receptacle, it presses against the tab. The tab may be configured to distribute force generated during an attempt to mate a misaligned plug away from thin wall portions of the insulative housing at an end of the slot. The tab may extend over a surface of the insulative housing beyond that thin wall portion and may be recessed into the housing.Type: GrantFiled: July 1, 2022Date of Patent: September 17, 2024Assignee: Amphenol East Asia Ltd.Inventor: Lo-Wen Lu
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Publication number: 20240287751Abstract: A method and device for optimizing regulation of reservoir sediment discharging, comprises: determining a relation curve between a dam front water depth and a reservoir capacity; determining a time length by which a sediment peak is propagated to the front of a dam and a time length by which the sediment peak lags behind a flood peak at the front of the dam based on the relation curve and the hydrologic features; determining another relation curve between a sediment peak attenuation rate and a sediment concentration of the sediment peak, and a time length by which the sediment peak subjected to a man-made flood wave is propagated to the front of the dam; and acquiring a real-time sediment concentration, and generating the man-made flood wave based on the time length by which the sediment peak is propagated to the front of the dam and the another relation curve.Type: ApplicationFiled: November 8, 2023Publication date: August 29, 2024Inventors: Bangwen Zhang, Anjun Deng, Dangwei Wang, Wen Lu, Hongling Shi, Huifang Liu, Hejing Zhao, Qin Lu, Zhandi Dong, Maohua Le, Yiqin Xie, Ke Ni
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Publication number: 20240275060Abstract: The present disclosure provides an electronic device. The electronic device includes a signal transmission structure and a circuit. The signal transmission structure defines a waveguide. The signal transmission structure defines a plurality of first apertures. The circuit is configured to adjust a geometric profile of at least one of the plurality of first apertures to control a frequency of an electromagnetic wave radiated from the first apertures.Type: ApplicationFiled: February 10, 2023Publication date: August 15, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
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Publication number: 20240275061Abstract: The present disclosure provides an electronic device. The electronic device includes a radio frequency (RF) circuit region and an antenna region. The RF circuit region has a first circuit density. The antenna region includes a circuit structure. The circuit structure defines a waveguide. The circuit structure has a second circuit density less than the first circuit density.Type: ApplicationFiled: February 10, 2023Publication date: August 15, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Shao-En HSU, Huei-Shyong CHO, Shih-Wen LU
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Patent number: 12057401Abstract: A semiconductor device including a substrate having a NMOS region and a PMOS region; a metal gate extending continuously along a first direction from the NMOS region to the PMOS region on the substrate; a first source/drain region extending along a second direction adjacent to two sides of the metal gate on the NMOS region; a second source/drain region extending along the second direction adjacent to two sides of the metal gate on the PMOS region; a first contact plug landing on the second source/drain region adjacent to one side of the metal gate; a second contact plug landing on the second source/drain region adjacent to another side of the metal gate; and a third contact plug landing directly on a portion of the metal gate on the PMOS region and between the first contact plug and the second contact plug.Type: GrantFiled: July 27, 2023Date of Patent: August 6, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Shih-Cheng Chen, Li-Hsuan Ho, Tsuo-Wen Lu, Shih-Hao Liang, Tsung-Hsun Wu, Po-Jen Chuang, Chi-Mao Hsu
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Patent number: 12046596Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.Type: GrantFiled: October 6, 2021Date of Patent: July 23, 2024Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ping-Hung Chiang
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Publication number: 20240241436Abstract: Methods and systems for determining a mask rule check violation (MRC) associated with a mask feature using a detector having geometric properties corresponding to the MRC. The detector (e.g., elliptical shaped) is configured to include a curved portion to detect a curvature violation, include an enclosed area (e.g., a fully enclosed area or a partially enclosed area having an opening), include a predefined orientation axis configured to guide relative positioning of the detector with a mask feature, and include a length to detect a critical dimension violation. The orientation axis of the detector is aligned with a normal axis at a location on the mask feature. Based on the orientation axis aligned with the normal axis of the mask feature, an MRC violation is determined corresponding to a region of the mask feature that intersects the enclosed area.Type: ApplicationFiled: May 10, 2022Publication date: July 18, 2024Applicant: ASML NETHERLANDS B.V.Inventors: Xingyue PENG, Rafael C. HOWELL, Yen Wen LU, Xiaorui CHEN
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Publication number: 20240243004Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A first trench isolation structure is disposed in the substrate between the first device region and the second device region. The first trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is lower than the second bottom surface. The first trench isolation structure includes a first top surface within the first device region and a second top surface within the second device region. The first top surface is coplanar with the second top surface.Type: ApplicationFiled: February 13, 2023Publication date: July 18, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Ling Wang, Ping-Hung Chiang, Ta-Wei Chiu, Chia-Wen Lu, Wei-Lun Huang, Yueh-Chang Lin
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Patent number: 12031870Abstract: The present invention provides a sensor assembly including housing; a sensor, disposed in the housing; a conductive member, having an inner portion located inside the housing and an outer portion located outside the housing. The outer portion receives a physical quantity from a component to be sensed and transmits the physical quantity to the sensor through the inner portion, so that the sensor senses the physical quantity and generates a sensing signal; a wireless communication module, receiving the sensing signal and transmits an output signal corresponding to the sensing signal. The invention also provides a method for using a sensor assembly as above.Type: GrantFiled: November 6, 2022Date of Patent: July 9, 2024Assignee: Aktiebolaget SKFInventors: Zhichao Hong, Wen Lu, Wei Yang
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Publication number: 20240221155Abstract: An eye image capturing and processing device is provided. The device includes a portable user terminal body and an application program installed in the portable user terminal body. The portable user terminal body has thereon an image capturing module for capturing an eye image of a user to generate instant image data. The application program receives the instant image data and performs a data processing procedure, and takes an automatic selfie or generates an indication signal to instruct the user to take a manual selfie when a preset condition is satisfied, thereby generating a to-be-diagnosed image corresponding to the eye of the user.Type: ApplicationFiled: December 28, 2023Publication date: July 4, 2024Inventors: CHENG-CHUN CHANG, Po-Wen Lu
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Publication number: 20240215875Abstract: A wearable device and a method for selecting and interpreting light intensity data values applicable thereto. The wearable device includes a light emitting unit and a spectrum sensing unit. The method includes steps of: controlling the light-emitting unit to simultaneously emit a mixed light including multiple spectrum frequency bands to enter inside skin of the user; controlling the spectrum sensing unit to sense the intensity of an outgoing light from inside skin of the user at a series of sampling time to generate a spectrum data set including a plurality of groups of frequency band-light intensity data values; and selecting at least one of a first group of frequency band-light intensity data values satisfying a signal quality index in the spectrum data set to perform a data interpretation at a first judgment time point.Type: ApplicationFiled: December 29, 2023Publication date: July 4, 2024Inventors: CHENG-CHUN CHANG, PO-WEN LU
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Publication number: 20240188823Abstract: An intraocular pressure detecting device includes the following elements. A force-applying element is adapted to apply a force to a target surface on a cornea of an eyeball in a direction, so that the target surface is deformed. A force-sensing element, coupled to the force-applying element, is adapted to sense the force applied by the force-applying element in the direction. A displacement-sensing element, coupled to the force-applying element, is adapted to sense a displacement of the force-applying element in the direction. A processing element is electrically connected to the force-sensing element and the displacement-sensing element to obtain a relationship curve between applied force and displacement. In particular, the processing element analyzes the relationship curve to obtain a characteristic critical point, and obtains an intraocular pressure value of the eyeball according to the applied force corresponding to the characteristic critical point.Type: ApplicationFiled: December 12, 2022Publication date: June 13, 2024Applicant: Industrial Technology Research InstituteInventors: De-Yi Chiou, Chi-Shen Chang, Da-Wen Lu
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Publication number: 20240186223Abstract: A semiconductor device package includes a substrate and a conductive lid. The conductive lid is disposed within the substrate. The conductive lid defines a waveguide having a cavity. The waveguide is configured to transmit a signal from a first electronic component to a second electronic component through the cavity.Type: ApplicationFiled: February 13, 2024Publication date: June 6, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventor: Shih-Wen LU
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Patent number: 11997783Abstract: The present disclosure provides an electronic device. The electronic device includes a first insulating layer, a first antenna pattern, a second insulating layer, and a second antenna pattern. The first antenna pattern is configured to operate at a first frequency and at least partially disposed over the first insulating layer. The second insulating layer is disposed over the first insulating layer. The second antenna pattern is configured to operate at a second frequency different from the first frequency and at least partially disposed over the second insulating layer. A dielectric constant of the first insulating layer is different from a dielectric constant of the second insulating layer.Type: GrantFiled: May 27, 2022Date of Patent: May 28, 2024Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Po-An Lin, Huei-Shyong Cho, Shih-Wen Lu
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Publication number: 20240162612Abstract: The present disclosure provides an electronic device. The electronic device includes a first transceiving element, a second transceiving element disposed over the first transceiving element, and a radiating structure configured to radiate a first EM wave having a lower frequency and a second EM wave having a higher frequency. The first transceiving element and the second transceiving element are collectively configured to provide a higher gain or bandwidth for the first EM wave than for the second EM wave.Type: ApplicationFiled: November 10, 2022Publication date: May 16, 2024Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Po-An LIN, Guan-Wei CHEN, Shih-Wen LU
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Publication number: 20240162833Abstract: A power supply unit supplies power to a load, and the power supply unit includes a power factor corrector, a DC conversion module, and an isolated conversion module. The power factor corrector is plugged into a first main circuit board and converts an AC power into a DC power. The DC conversion module is plugged into the first main circuit board and converts the DC power into a main power. The isolated conversion module includes a bus capacitor, the bus capacitor is coupled to the DC conversion module through a first power copper bar, and coupled to the power factor corrector through a second power copper bar. The first power copper bar and the second power copper bar are arranged on a side opposite to the first main circuit board, and are arranged in parallel with the first main circuit board.Type: ApplicationFiled: November 13, 2023Publication date: May 16, 2024Inventors: Yi-Sheng CHANG, Cheng-Chan HSU, Chia-Wei CHU, Chun-Yu YANG, Deng-Cyun HUANG, Yi-Hsun CHIU, Chien-An LAI, Yu-Tai WANG, Chi-Shou HO, Zhi-Yuan WU, Ko-Wen LU
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Patent number: 11982500Abstract: A heat sink includes a heat conduction portion and a heat dissipation portion. The heat conduction portion is a flat plate with two main surfaces parallel with each other and a plurality of side surfaces. One of the two main surfaces is a contacting surface contacting a heat source. The heat dissipation portion is extended outward from at least one of the plurality of side surfaces of the heat conduction portion. The heat dissipation portion includes a plurality of first branches and a plurality of second branches. Each of the first branches is a flat plate and has two opposite main surfaces and four side surfaces. The two opposite main surfaces of each of the first branches are parallel to the two main surfaces of the heat conduction portion. The second branches are extended from the first branches and parallel to the heat conduction portion.Type: GrantFiled: March 23, 2022Date of Patent: May 14, 2024Assignee: DELTA ELECTRONICS, INC.Inventor: Chao-Wen Lu