Patents by Inventor Wen Lu

Wen Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11734490
    Abstract: A method to determine a curvilinear pattern of a patterning device that includes obtaining (i) an initial image of the patterning device corresponding to a target pattern to be printed on a substrate subjected to a patterning process, and (ii) a process model configured to predict a pattern on the substrate from the initial image, generating, by a hardware computer system, an enhanced image from the initial image, generating, by the hardware computer system, a level set image using the enhanced image, and iteratively determining, by the hardware computer system, a curvilinear pattern for the patterning device based on the level set image, the process model, and a cost function, where the cost function (e.g., EPE) determines a difference between a predicted pattern and the target pattern, where the difference is iteratively reduced.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 22, 2023
    Assignee: ASML NETHERLANDS B.V.
    Inventors: Quan Zhang, Been-Der Chen, Rafael C. Howell, Jing Su, Yi Zou, Yen-Wen Lu
  • Patent number: 11728585
    Abstract: An electrical connector includes a housing having a wall bounding, at least in part, an opening in which a plurality of terminals are exposed and a shell configured to encircle an outer surface of the wall. The shell may include: guide portions, a plurality of first portions configured to conform with the outer surface of the wall, a plurality of second portions spaced apart from the outer surface of the wall, and a plurality of hook portions configured to engage with an edge of the wall. The hook portions may be opposite the guide portions. Second portions, spaced from the outer surface of the wall, may be distributed around the bounding wall and may have different sizes to receive different projections from the plug, both preventing insertion of the plug in an incorrect orientation and counterbalancing the force on the connector housing during mating of a plug to the connector.
    Type: Grant
    Filed: June 15, 2021
    Date of Patent: August 15, 2023
    Assignee: Amphenol East Asia Ltd.
    Inventor: Lo-Wen Lu
  • Patent number: 11721110
    Abstract: A method for providing driving assistance is implemented by a driving assistance system and includes the steps of: continuously capturing images of the surrounding environment of the vehicle; performing an image processing procedure on at least one of the images; determining whether a traffic sign indicating a message is detected in the at least one of the images, and whether additional information indicating a condition associated with the message is detected with respect to the traffic sign; determining whether an alert action is to be executed based on the message and a current condition associated with the vehicle; and when the determination is affirmative, executing the alert action.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: August 8, 2023
    Assignee: MiTAC Digital Technology Corporation
    Inventor: Chieh-Wen Lu
  • Publication number: 20230244152
    Abstract: A method for determining a likelihood that an assist feature of a mask pattern will print on a substrate. The method includes obtaining (i) a plurality of images of a pattern printed on a substrate and (ii) variance data the plurality of images of the pattern; determining, based on the variance data, a model configured to generate variance data associated with the mask pattern; and determining, based on model-generated variance data for a given mask pattern and a resist image or etch image associated with the given mask pattern, the likelihood that an assist feature of the given mask pattern will be printed on the substrate. The likelihood can be applied to adjust one or more parameters related to a patterning process or a patterning apparatus to reduce the likelihood that the assist feature will print on the substrate.
    Type: Application
    Filed: June 17, 2021
    Publication date: August 3, 2023
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jen-Shiang WANG, Pengcheng YANG, Jiao HUANG, Yen-Wen LU, Liang LIU, Chen ZHANG
  • Publication number: 20230237973
    Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.
    Type: Application
    Filed: January 26, 2022
    Publication date: July 27, 2023
    Inventor: Chih-Wen Lu
  • Publication number: 20230231035
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A first recess and a second recess are formed in a first region and a second region of a semiconductor substrate, respectively. A bottom surface of the first recess is lower than a bottom surface of the second recess in a vertical direction. A first gate oxide layer and a second gate oxide layer are formed concurrently. At least a portion of the first gate oxide layer is formed in the first recess, and at least a portion of the second gate oxide layer is formed in the second recess. A removing process is performed for removing a part of the second gate oxide layer. A thickness of the second gate oxide layer is less than a thickness of the first gate oxide layer after the removing process.
    Type: Application
    Filed: February 17, 2022
    Publication date: July 20, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ta-Wei Chiu, Ping-Hung Chiang
  • Patent number: 11705084
    Abstract: A high-speed buffer amplifier includes an input stage including a first channel coupled to receive differential inputs and a second channel coupled to receive the differential inputs; a middle stage including a first current source coupled to receive outputs of the second channel and electrically connected to power, a second current source coupled to receive outputs of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and an output stage coupled to the middle stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source, and configured to bypass the floating current source.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: July 18, 2023
    Assignee: Himax Technologies Limited
    Inventor: Chih-Wen Lu
  • Publication number: 20230223306
    Abstract: Semiconductor device and method of fabricating the same, the semiconductor device includes a substrate, a first transistor, a second transistor, a third transistor, and a plurality of shallow trench isolations. The first transistor is disposed in a medium-voltage region and includes a first plane, a first gate dielectric layer, and a first gate electrode. The second transistor is disposed in a boundary region and includes a second plane, a second gate dielectric layer, and a second gate electrode. The third transistor is disposed in a lower-voltage region and includes a third plane, a third gate dielectric layer, and a third gate electrode. The shallow trench isolations are disposed in the substrate, wherein top surfaces of the shallow trench isolations in the medium-voltage region, the boundary region and the low-voltage region are coplanar with top surfaces of the first gate dielectric layer and the second gate dielectric layer.
    Type: Application
    Filed: February 15, 2022
    Publication date: July 13, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ta-Wei Chiu, Ping-Hung Chiang, Chia-Wen Lu, Chia-Ling Wang, Wei-Lun Huang
  • Publication number: 20230210522
    Abstract: An endoscope device including an endoscope body, a suture device, and a needle. The endoscope body has a proximal portion and a distal portion opposite each other and includes a working channel. The suture device includes a first arm and a second arm opposite each other. The working channel connects the proximal portion and the distal portion. The first arm and the second arm extend toward a distal direction. At least one of the first arm and the second arm are pivotally connected to the distal portion and can be opened or closed with respect to the other. The operation method thereof is also provided.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 6, 2023
    Inventor: Po-Wen LU
  • Publication number: 20230216375
    Abstract: A micro fan is provided. The micro fan includes a rotor and a stator. The stator includes a plurality of axial induced coil units and a circuit board. The axial induced coil units are respectively preformed as a plurality of stator magnetic pole units, and are coupled to the circuit board. At least one of the coil units includes a coil and insulation material. The insulation material is block-shaped and covers at least a portion of the coil, and the central axis of the coil is parallel to the shaft of the rotor.
    Type: Application
    Filed: March 10, 2023
    Publication date: July 6, 2023
    Inventors: Chin-Chun LAI, Chao-Wen LU
  • Publication number: 20230207620
    Abstract: A semiconductor structure includes a substrate having a first device region and a second device region in proximity to the first device region. A trench isolation structure is disposed in the substrate between the first device region and the second device region. The trench isolation structure includes a first bottom surface within the first device region and a second bottom surface within the second device region. The first bottom surface is coplanar with the second bottom surface.
    Type: Application
    Filed: January 18, 2022
    Publication date: June 29, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Ling Wang, Ping-Hung Chiang, Wei-Lun Huang, Chia-Wen Lu, Ta-Wei Chiu
  • Publication number: 20230185183
    Abstract: A method for improving a design of a patterning device. The method includes (i) obtaining mask points of a design of a mask feature, wherein the mask feature corresponds to a target feature in a target pattern to be printed on a substrate; and (ii) adjusting locations of the mask points to generate a modified design of the mask feature based on the adjusted mask points.
    Type: Application
    Filed: May 7, 2021
    Publication date: June 15, 2023
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jiuning HU, Jun YE, Yen-Wen LU
  • Patent number: 11670846
    Abstract: A semiconductor device package includes a substrate, a first antenna pattern and a second antenna pattern. The substrate has a first surface and a second surface opposite to the first surface. The first antenna pattern is disposed over the first surface of the substrate. The first antenna pattern has a first bandwidth. The second antenna pattern is disposed over the first antenna pattern. The second antenna pattern has a second bandwidth different from the first bandwidth. The first antenna pattern and the second antenna pattern are at least partially overlapping in a direction perpendicular to the first surface of the substrate.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 6, 2023
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Shao-En Hsu, Huei-Shyong Cho, Shih-Wen Lu
  • Patent number: 11668947
    Abstract: Embodiment of present invention provide a wavelength division multiplexing (WDM) module. The WDM module includes a substrate having a first side and a second side opposing the first side, wherein the first side includes a transpassing region coated with an anti-reflective (AR) film and a reflective region coated with a high-reflective (HR) film, and the second side includes multiple ports of optical paths; multiple WDM filters attached to the multiple ports at the second side of the substrate, wherein surfaces of the WDM filters attached to the substrate are coated with WDM films; and at least one reflector attached to the second side of the substrate in a space between the multiple WDM filters, wherein the reflector has a first surface attached to the substrate and a second surface, opposing the first surface, that has a convex shape and coated with a high-reflective (HR) coating.
    Type: Grant
    Filed: January 11, 2021
    Date of Patent: June 6, 2023
    Assignee: Auxora (Shenzhen) Inc.
    Inventors: Jinghui Li, Qingming Zhang, Wen Lu, Yangjie Zheng
  • Publication number: 20230168128
    Abstract: The present invention provides a sensor assembly including housing; a sensor, disposed in the housing; a conductive member, having an inner portion located inside the housing and an outer portion located outside the housing. The outer portion receives a physical quantity from a component to be sensed and transmits the physical quantity to the sensor through the inner portion, so that the sensor senses the physical quantity and generates a sensing signal; a wireless communication module, receiving the sensing signal and transmits an output signal corresponding to the sensing signal.
    Type: Application
    Filed: November 6, 2022
    Publication date: June 1, 2023
    Inventors: Zhichao HONG, Wen LU, Wei YANG
  • Publication number: 20230137097
    Abstract: A method including: obtaining data based an optical proximity correction for a spatially shifted version of a training design pattern; and training a machine learning model configured to predict optical proximity corrections for design patterns using data regarding the training design pattern and the data based on the optical proximity correction for the spatially shifted version of the training design pattern.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 4, 2023
    Applicant: ASML NETHERLANDS B.V.
    Inventors: Jing Su, Yen-Wen Lu, Ya Luo
  • Publication number: 20230106501
    Abstract: The present invention provides a semiconductor memory device including a substrate, a plurality of capacitors and a supporting layer disposed on the substrate, wherein each of the capacitors is connected with at least one of the adjacent capacitors through the supporting layer. Each of the capacitors includes first electrodes, a high-k dielectric layer and a second electrode, and the high-k dielectric layer is disposed between the first electrodes and the second electrode. Due to the supporting layer directly contacts the high-k dielectric layer through a surface thereof, and the high-k dielectric layer completely covers the surface, the second electrode may be formed directly within openings with an enlarged dimension. Accordingly, the process difficulty of performing the deposition and etching processes within the openings may be reduced, and the capacitance of the capacitors is further increased.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Applicant: Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pei-Ting Tsai, Yu-Cheng Tung, Tsuo-Wen Lu, Min-Teng Chen, Tsung-Wen Chen
  • Publication number: 20230080968
    Abstract: The invention provides a method for forming a semiconductor structure, which comprises providing a substrate, sequentially a first groove and a second groove are formed in the substrate, the depth of the first groove is different from the depth of the second groove, a first oxide layer is formed in the first groove, a second oxide layer is formed in the second groove, an etching step is performed to remove part of the first oxide layer, a first gate structure is formed on the first oxide layer, and a second gate structure is formed on the second oxide layer.
    Type: Application
    Filed: October 6, 2021
    Publication date: March 16, 2023
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Wei-Lun Huang, Chia-Ling Wang, Chia-Wen Lu, Ping-Hung Chiang
  • Publication number: 20230057327
    Abstract: The present disclosure provides an electronic module including a circuit including a transmitting part and a receiving part physically separated from the transmitting part. The electronic module also includes an element isolated from the circuit and configured to block electrical interference between the transmitting part and the receiving part.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Shih-Wen LU, Chun-Jen CHEN, Po-Hsiang TSENG, Hsin-Han LIN, Ming-Lun YU
  • Publication number: 20230055717
    Abstract: The present disclosure relates to an electronic device that includes a first radiating element configured to radiate a first electromagnetic wave and a second radiating element configured to radiate a second electromagnetic wave. A first radiation pattern of the first electromagnetic wave is configured to be adjusted, and a second radiation pattern of the second electromagnetic wave is configured to be fixed.
    Type: Application
    Filed: August 19, 2021
    Publication date: February 23, 2023
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventor: Shih-Wen LU