Patents by Inventor Wen Su

Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • INTEGRATED CHIP WITH IMPROVED LATCH-UP IMMUNITY
    Publication number: 20210280584
    Abstract: Various embodiments of the present disclosure are directed towards an integrated chip (IC) having a device section and a pick-up section. The IC includes a semiconductor substrate. A first fin of the semiconductor substrate is disposed in the device section. A second fin of the semiconductor substrate is disposed in the pick-up section and laterally spaced from the first fin in a first direction. A gate structure is disposed in the device section and laterally spaced from the second fin in the first direction. The gate structure extends laterally over the semiconductor substrate and the first fin in a second direction perpendicular to the first direction. A pick-up region is disposed on the second fin. The pick-up region continuously extends from a first sidewall of the second fin to a second sidewall of the second fin. The first sidewall is laterally spaced from the second sidewall in the first direction.
    Type: Application
    Filed: March 4, 2020
    Publication date: September 9, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Wen-Chun Keng, Chih-Chuan Yang, Shih-Hao Lin
  • SRAM Speed and Margin Optimization Via Spacer Tuning
    Publication number: 20210272966
    Abstract: An N-type metal oxide semiconductor (NMOS) transistor includes a first gate and a first spacer structure disposed on a first sidewall of the first gate in a first direction. The first spacer structure has a first thickness in the first direction and measured from an outermost point of an outer surface of the first spacer structure to the first sidewall. A P-type metal oxide semiconductor (PMOS) transistor includes a second gate and a second spacer structure disposed on a second sidewall of the second gate in the first direction and measured from an outermost point of an outer surface of the second spacer structure to the second sidewall. The second spacer structure has a second thickness that is greater than the first thickness. The NMOS transistor is a pass-gate of a static random access memory (SRAM) cell, and the PMOS transistor is a pull-up of the SRAM cell.
    Type: Application
    Filed: September 29, 2020
    Publication date: September 2, 2021
    Inventors: Shih-Hao Lin, Chih-Chuan Yang, Hsin-Wen Su, Kian-Long Lim, Chien-Chih Lin
  • CHEMICAL DIRECT PATTERN PLATING METHOD
    Publication number: 20210272910
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Application
    Filed: May 3, 2021
    Publication date: September 2, 2021
    Inventors: Wen-Jiun LIU, Chen-Yuan Kao, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Method of Forming an Interconnect Structure Having an Air Gap and Structure Thereof
    Publication number: 20210265272
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Application
    Filed: May 10, 2021
    Publication date: August 26, 2021
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR FABRICATING THE SAME
    Publication number: 20210249529
    Abstract: A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a patterned mask on the buffer layer; using the patterned mask to remove the buffer layer for forming ridges and a damaged layer on the ridges; removing the damaged layer; forming a barrier layer on the ridges; and forming a p-type semiconductor layer on the barrier layer.
    Type: Application
    Filed: March 4, 2020
    Publication date: August 12, 2021
    Inventors: Po-Wen Su, Ming-Hua Chang, Shui-Yen Lu
  • CONTROLLING TRAP FORMATION TO IMPROVE MEMORY WINDOW IN ONE-TIME PROGRARM DEVICES
    Publication number: 20210242222
    Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.
    Type: Application
    Filed: February 4, 2020
    Publication date: August 5, 2021
    Inventors: Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang, Yu-Kuan Lin, Shih-Hao Lin
  • Identifying advertisements embedded in videos
    Patent number: 11074457
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for identifying advertisements in a video. The method includes obtaining a plurality of copies of the video and processing each of the plurality of copies of the video, wherein the processing identifies a plurality of iframes in each of the plurality of copies of the video. The method also includes comparing the plurality of iframes of each of the plurality of copies of the video. The method further includes identifying one or more common portions of each of the plurality of copies of the video one or more advertisement in the video, based on the comparison.
    Type: Grant
    Filed: April 17, 2019
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ying-Chen Yu, Jeff Hsueh-Chang Kuo, Chih-Wen Su, June-Ray Lin
  • System and method for adaptive video
    Patent number: 11076207
    Abstract: A method, computer program product, and computer system for receiving, by a computing device, one or more user preferences for a video clip. The one or more user preferences may be matched with one or more branches of the video clip, wherein each of the one or more branches may include one or more segments of the video clip. The one or more segments of the video clip may be selected from the one or more branches based upon, at least in part, matching the one or more user preferences with the one or more branches of the video clip. The video clip may be composed based upon, at least in part, the one or more user preferences.
    Type: Grant
    Filed: November 2, 2018
    Date of Patent: July 27, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Chih-Wen Su, Jeff Hsueh-Chang Kuo, Ying-Chen Yu
  • Structure and process of integrated circuit having latch-up suppression
    Patent number: 11062963
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.
    Type: Grant
    Filed: July 25, 2019
    Date of Patent: July 13, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Interconnect structure having a carbon-containing barrier layer
    Patent number: 11062909
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Multi-antenna system and electronic device thereof
    Patent number: 11056770
    Abstract: A multi-antenna system includes a conductive plane with four adjacent sides, a main antenna unit disposed on any one of the four sides, a first secondary antenna unit disposed on any one of the four side, a second secondary antenna unit disposed on any one of the four sides of the conductive plane except the side on which the main antenna unit is disposed, a switching circuit disposed on the conductive plane and is selectively electrically connected to the first secondary antenna unit or the second secondary antenna unit and a wireless communications module disposed on the conductive plane and electrically connected to the switching circuit and the main antenna unit. The first secondary antenna unit is spaced apart from the main antenna unit by a spacing, where the spacing is greater than 0.5 times a wavelength distance of a low-frequency operating frequency of the multi-antenna system.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: July 6, 2021
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Saou-Wen Su, Wei-Hsuan Chang
  • Cut metal gate in memory macro edge and middle strap
    Patent number: 11043595
    Abstract: A semiconductor device includes a memory macro having first and second well pick-up (WPU) areas along first and second edges of the memory macro, respectively, and memory bit areas between the first and the second WPU areas. The first and second WPU areas are oriented lengthwise generally along a first direction. In each of the first and second WPU areas, the memory macro includes n-type wells and p-type wells arranged alternately along the first direction with a well boundary between each of the n-type wells and the adjacent p-type well. The memory macro further includes active regions; an isolation structure; gate structures, and a first dielectric layer that is disposed at each of the well boundaries. From a top view, the first dielectric layer extends generally along a second direction perpendicular to the first direction and through all the gate structures in the first and the second WPU areas.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: June 22, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsin-Wen Su, Yu-Kuan Lin, Chih-Chuan Yang, Chang-Ta Yang, Shih-Hao Lin
  • DISPLAY DEVICE AND ASSEMBLING METHOD THEREOF
    Publication number: 20210158767
    Abstract: A display device includes a backlight module, and the backlight module includes a light-guiding plate, a light-emitting assembly, and an adhesive member. The light-emitting assembly is disposed correspondingly to the light-guiding plate, and includes a substrate and a plurality of light-emitting elements. The substrate includes a component arrangement region and a planar region in a top view, and includes a base material layer, a filled layer and a protection layer in a sectional view. A thickness of the protection layer is greater than 0 ?m and less than 30 ?m. The light-emitting elements are located on the component arrangement region. The adhesive member connects the light-guiding plate and the planar region of the substrate. An assembling method of the display device is also provided. This disclosure can improve the non-uniform brightness issue (hotspots) or enhance the optical performance.
    Type: Application
    Filed: February 1, 2021
    Publication date: May 27, 2021
    Inventors: CHUNG-CHUN KUO, CHUN-FANG CHEN, HUI-WEN SU, WEI-YUAN CHEN, CHUNG-YU CHENG
  • Physical vapor deposition process for semiconductor interconnection structures
    Patent number: 11018055
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: May 25, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Scooter
    Patent number: D920166
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni, Ting-Ping Ku
  • Scooter
    Patent number: D920167
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Scooter
    Patent number: D920200
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 25, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Scooter
    Patent number: D920851
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: June 1, 2021
    Assignee: Gogoro Inc.
    Inventors: Sung-Fu Wang, Hsin-Wen Su, Chien-Chih Weng, Hsi-Wen Chen, Ching-Chang Ni
  • Motor scooter
    Patent number: D928040
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 17, 2021
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Song-Fu Wang, Hsin-Wen Su, Hsi-Wen Chen, Chien-Chih Weng
  • Motor scooter
    Patent number: D928666
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: August 24, 2021
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Song-Fu Wang, Hsin-Wen Su, Hsi-Wen Chen, Chien-Chih Weng