Abstract: A method of forming an integrated circuit, including forming a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side on a semiconductor substrate, forming a first fin active region extruded from the N-well and a second fin active region extruded from the P-well, forming a first isolation feature inserted between and vertically extending through the N-well and the P-well, and forming a second isolation feature over the N-well and the P-well and laterally contacting the first and the second fin active regions.

Abstract: Semiconductor structures and methods of the forming the same are provided. A semiconductor structure according to the present disclosure includes a source feature and a drain feature, an active region between the source feature and the drain feature, a gate structure over the active region, a frontside interconnect structure disposed over the source feature, the drain feature, and the gate structure, a backside interconnect structure disposed below the source feature, the drain feature, and the gate structure, and a storage element disposed in the backside interconnect structure.

Abstract: Methods of forming a semiconductor device are provided. A method according to the present disclosure includes forming, over a workpiece, a dummy gate stack comprising a first semiconductor material, depositing a first dielectric layer over the dummy gate stack using a first process, implanting the workpiece with a second semiconductor material different from the first semiconductor material, annealing the dummy gate stack after the implanting, and replacing the dummy gate stack with a metal gate stack.

Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

Abstract: A magnetic device structure is provided. In some embodiments, the structure includes one or more first transistors, a magnetic device disposed over the one or more first transistors, a plurality of magnetic columns surrounding sides of the one or more first transistors and the magnetic device, a first magnetic layer disposed over the magnetic device and in contact with the plurality of magnetic columns, and a second magnetic layer disposed below the one or more first transistors and in contact with the plurality of magnetic columns.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Abstract: An eccentric wheel adjustment device includes a hub (1), an adjustment disk (2) and a release structure (3). The hub (1) has an axle portion (10) eccentrically arranged and an inner ring portion (11) formed around the axle portion (10). The adjustment disk (2) has a disk seat (20) for the hub (1) being pivotally disposed thereon and a positioning member (21) for positioning the hub (1) on the disk seat (20). The positioning member (21) has an outer ring portion (210) for aligning the inner ring portion (11) of the hub (1) in the outer ring portion (210). The release structure (3) includes a limiting block (30) and a switch member (31) driving the limiting block (30) to act so as to drive the limiting block (30) to straddle between the hub (1) and the adjustment disk (2) or to move back to the inner ring portion (11).

Abstract: A semiconductor memory device includes a first word line formed over a first active region. In some embodiments, a first metal line is disposed over and perpendicular to the first word line, where the first metal line is electrically connected to the first word line using a first conductive via, and where the first conductive via is disposed over the first active region. In some examples, the semiconductor memory device further includes a second metal line and a third metal line both parallel to the first metal line and disposed on opposing sides of the first metal line, where the second metal line is electrically connected to a source/drain region of the first active region using a second conductive via, and where the third metal line is electrically connected to the source/drain region of the first active region using a third conductive via.

Abstract: The present disclosure provides semiconductor device and methods of forming the same. A semiconductor device according to the present disclosure includes a gate structure, a source/drain feature adjacent the gate structure, a dielectric layer disclosed over the gate structure and the source/drain feature, a gate contact disposed in the dielectric layer and over the gate structure, and a source/drain contact disposed in the dielectric layer and over the source/drain feature. The dielectric layer is doped with a dopant and the dopant includes germanium or tin.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a Schottky diode, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate, wherein a first source/drain structure of the first transistor is electrically connected to a first source/drain structure of the second transistor. The Schottky diode is electrically connected to a gate structure of the first transistor. The first word line is electrically connected to the gate structure of the first transistor through the Schottky diode. The second word line is electrically connected to a gate structure of the second transistor. The bit line is electrically connected to a second source/drain structure of the second transistor.

Abstract: A semiconductor device is manufactured by modifying an electromagnetic field within a deposition chamber. In embodiments in which the deposition process is a sputtering process, the electromagnetic field may be modified by adjusting a distance between a first coil and a mounting platform. In other embodiments, the electromagnetic field may be adjusted by applying or removing power from additional coils that are also present.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

Abstract: The invention provides an input device including a holder, a first wheel, a slider, and a first pressure part. The first wheel is disposed on the holder, and includes a side surface, a circle center, and a segment adjusting structure. The segment adjusting structure is disposed on the side surface in a manner of surrounding the circle center. The slider is disposed on the holder, and is movable relative to the holder to move toward or away from the circle center. The first pressure part includes two first ends. One of the first ends is connected to the slider, and as the slider moves toward or away from the circle center, interference between the other first end and the segment adjusting structure is increased or reduced.

Abstract: An opening is formed through a dielectric material layer to physically expose a top surface of a conductive material portion in, or over, a substrate. A metallic nitride liner is formed on a sidewall of the opening and on the top surface of the conductive material portion. A metallic adhesion layer including an alloy of copper and at least one transition metal that is not copper is formed on an inner sidewall of the metallic nitride liner. A copper fill material portion may be formed on an inner sidewall of the metallic adhesion layer. The metallic adhesion layer is thermally stable, and remains free of holes during subsequent thermal processes, which may include reflow of the copper fill material portion. An additional copper fill material portion may be optionally deposited after a reflow process.

Abstract: In some embodiments, the present disclosure relates to a one-time program (OTP) memory cell. The OTP memory cell includes a read transistor and a program transistor neighboring the read transistor. The read transistor includes a read dielectric layer and a read gate electrode overlying the read dielectric layer. The program transistor includes a program dielectric layer and a program gate electrode overlying the program dielectric layer. The program transistor has a smaller breakdown voltage than the read transistor.

Abstract: The invention provides an input device including a holder, a first wheel, a slider, and a first pressure part. The first wheel is disposed on the holder, and includes a side surface, a circle center, and a segment adjusting structure. The segment adjusting structure is disposed on the side surface in a manner of surrounding the circle center. The slider is disposed on the holder, and is movable relative to the holder to move toward or away from the circle center. The first pressure part includes two first ends. One of the first ends is connected to the slider, and as the slider moves toward or away from the circle center, interference between the other first end and the segment adjusting structure is increased or reduced.

Abstract: A loop-like dual-antenna system is provided. The loop-like dual-antenna system includes a dielectric substrate having a first surface and a second surface opposite to each other. The loop radiating element includes a first radiating part with two ends and a second radiating part opposite to the first radiating part. A first signal source is disposed on the first surface of the dielectric substrate and electrically connected to two ends of the first radiating part. A grounding part is disposed on the second surface of the dielectric substrate and disposed on one side of the dielectric substrate away from the first signal source. A coupling matching element is disposed on the second surface of the dielectric substrate and adjacent to the grounding part, for coupling to and exciting the second radiating part. A second signal source, disposed on the second surface of the dielectric substrate, and electrically connected to the coupling matching element and the grounding part.

Abstract: A memory device includes a substrate, a first transistor and a second transistor, a first word line, a second word line, and a bit line. The first transistor and the second transistor are over the substrate and are electrically connected to each other, in which each of the first and second transistors includes first semiconductor layers and second semiconductor layers, a gate structure, and source/drain structures, in which the first semiconductor layers are in contact with the second semiconductor layers, and a width of the first semiconductor layers is narrower than a width of the second semiconductor layers. The first word line is electrically connected to the gate structure of the first transistor. The second word line is electrically connected to the gate structure of the second transistor. The bit line is electrically connected to a first one of the source/drain structures of the first transistor.