Patents by Inventor Wen Su

Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200058564
    Abstract: The present disclosure provides one embodiment of a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a n-type doped well (N-well) and a p-type doped well (P-well) disposed side by side; a first fin active region extruded from the N-well of the semiconductor substrate; a second fin active region extruded from the P-well of the semiconductor substrate; a first isolation feature formed on the N-well and the P-well and laterally contacting the first and second fin active regions, the first isolation feature having a first width; and a second isolation feature inserted between the N-well and the P-well, the second isolation feature having a second width less than the first width.
    Type: Application
    Filed: July 25, 2019
    Publication date: February 20, 2020
    Inventors: Kuo-Hsiu Hsu, Yu-Kuan Lin, Feng-Ming Chang, Hsin-Wen Su, Lien Jung Hung, Ping-Wei Wang
  • Publication number: 20200042103
    Abstract: A key module including a base, a circuit layer, at least one light-transmission key body, and a display panel is provided. The circuit layer is disposed at the base and has at least one input portion. The light-transmission key body has an abutting end and a pressing end opposite to each other. The abutting end abuts the base, and the light-transmission key body is adapted to be pressed downward by taking the abutting end as a rotation axis, such that the pressing end presses the input portion. The display panel is disposed at the base and has at least one display region, the display region is aligned with the light-transmission key body, and an image displayed on the display region by the display panel is changeable.
    Type: Application
    Filed: May 15, 2019
    Publication date: February 6, 2020
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Chih-Wen Su, Yu-Hsun Chen
  • Publication number: 20200025587
    Abstract: One or more processors track internet usage of a user. The tracking includes tracking a first user input into one or more websites using a keylogging subprogram. One or more processors analyze the first user input. Analyzing the first user input includes using machine learning to gain knowledge of one or more interests of the first user based on the first user input. One or more processors determine a proximity of the first user to at least one point of interest within a first threshold distance of the first user while the first user is mobile, match at least one interest of the one or more interests of the first user with one or more interests associated with the at least one point of interest, and provide a notification that the first user is within the first threshold distance of the at least one point of interest.
    Type: Application
    Filed: September 23, 2019
    Publication date: January 23, 2020
    Inventors: Li-Ju Chen, Jeff HC Kuo, Chih-Wen Su, Ying-Chen Yu
  • Publication number: 20200028236
    Abstract: An electronic device casing adapted to cover an antenna is provided. The electronic device casing includes a supporting layer and a carbon fiber layer. The carbon fiber layer is disposed on a surface of the supporting layer and includes a signal passing region having a plurality of slits and a plurality of microstructures separated by the slits. The signal passing region is adapted to cover the antenna, and a signal excited by the antenna is adapted to pass through the supporting layer and the slits so as to pass through the electronic device casing. An electronic device having the electronic device casing is further provided.
    Type: Application
    Filed: June 13, 2019
    Publication date: January 23, 2020
    Applicant: HTC Corporation
    Inventors: Ying-Hao Yeh, Sheng-Wen Su
  • Patent number: 10529575
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10522652
    Abstract: A semiconductor device and a method for fabricating the same are provided. A structure of the semiconductor device includes a substrate having a device region and an edge region. A plurality of device structures is formed on the substrate. An etching stop layer is disposed in the edge region of the substrate. The etching stop layer is converted from P-type dopants from an exposed surface layer of the substrate.
    Type: Grant
    Filed: September 12, 2018
    Date of Patent: December 31, 2019
    Assignee: United Microelectronics Corp.
    Inventors: Po-Wen Su, Chih-Wei Lin, Wei-Chih Lai, Tai-Yen Lin
  • Patent number: 10522399
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Publication number: 20190394160
    Abstract: The present invention discloses a method and apparatus for routing a message. Specifically, the method for example may comprise: receiving a message lacking a recipient address; searching for at least one recipient address based on a topic associated with the message; and sending the message to the at least one recipient address. The technology according to the example embodiments of the present invention provides a novel technology for routing a message to a recipient based on a topic associated with the message.
    Type: Application
    Filed: September 5, 2019
    Publication date: December 26, 2019
    Inventors: Li-Ju Chen, Yi-Hsin Cheng, Jeff HC Kuo, Ming Tung Lau, Wai Man Lee, Chih-Wen Su, Ying-Chen Yu
  • Patent number: 10508356
    Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.
    Type: Grant
    Filed: December 1, 2016
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
  • Patent number: 10505007
    Abstract: A semiconductor device includes a metal gate on a substrate, in which the metal gate includes a first work function metal (WFM) layer and the first WFM layer further includes a first vertical portion, a second vertical portion, wherein the first vertical portion and the second vertical portion comprise different heights, and a first horizontal portion connecting the first vertical portion and the second vertical portion.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: December 10, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Wen-Yen Huang, Kuan-Ying Lai, Shui-Yen Lu
  • Patent number: 10504832
    Abstract: A method of forming a semiconductor structure includes the steps: providing a substrate; forming a dielectric over the substrate; forming an opening recessed under a top surface of the dielectric; forming a barrier layer on a sidewall of the opening; performing a physical vapor deposition (PVD) to form a copper layer over the barrier layer, a corner of the opening intersecting with the top surface and the top surface with a predetermined resputter ratio so that the ratio of the thickness of the copper layer on the barrier layer and the thickness of the copper layer over the top surface is substantially greater than 1.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: December 10, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ken-Yu Chang, Hung-Wen Su
  • Patent number: 10483158
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 19, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Publication number: 20190348003
    Abstract: A display device includes a backlight module, and the backlight module includes a light-guiding plate, a light-emitting assembly, and an adhesive member. The light-emitting assembly is disposed corresponding to the light-guiding plate and includes a substrate and a plurality of light-emitting elements. The substrate includes a first surface, and the first surface includes a component arrangement region and a planar region. A first gap is formed between the planar region and the component arrangement region, and the planar region and the component arrangement region are electrically isolated from each other. The light-emitting elements are disposed on the component arrangement region. The adhesive member connects the light-guiding plate and the planar region. An assembling method of the display device is also provided. This disclosure can improve the non-uniform brightness issue (hotspots) or enhance the optical performance.
    Type: Application
    Filed: May 1, 2019
    Publication date: November 14, 2019
    Inventors: Chung-Chun KUO, Chun-Fang CHEN, Hui-Wen SU, Wei-Yuan CHEN, Chung-Yu CHENG
  • Publication number: 20190326220
    Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.
    Type: Application
    Filed: July 1, 2019
    Publication date: October 24, 2019
    Inventors: Szu-Ping Tung, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20190327080
    Abstract: An example operation may include one or more of configuring a blockchain network comprising first and second blockchain nodes, providing, by the first blockchain node, a data reference to the second blockchain node, accessing a document, by the second blockchain node, from the first blockchain node, and providing by the second blockchain node, a proof of receipt for the document to a shared blockchain ledger.
    Type: Application
    Filed: April 24, 2018
    Publication date: October 24, 2019
    Inventors: Chih-Hsiung Liu, Joey H.Y. Tseng, Chih-Wen Su, June-Ray Lin, Gary P. Noble
  • Patent number: 10438846
    Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 8, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Nai-Hao Yang, Hung-Wen Su, Kuan-Chia Chen
  • Publication number: 20190304792
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: June 3, 2019
    Publication date: October 3, 2019
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10425374
    Abstract: Routing a message to a recipient based on a topic associated with the message may include: receiving a message lacking a recipient address; searching for at least one recipient address based on a topic associated with the message; and sending the message to the at least one recipient address.
    Type: Grant
    Filed: April 10, 2013
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Ju Chen, Yi-Hsin Cheng, Jeff H C Kuo, Ming Tung Lau, Wai Man Lee, Chih-Wen Su, Ying-Chen Yu
  • Patent number: 10422657
    Abstract: One or more processors analyze at least one first user input. One or more processors determine one or more interests of a first user based, at least in part, on the at least one first user input. One or more processors determine a proximity of the first user to one or more points of interest within a first threshold distance of the first user while the first user is mobile. One or more processors match at least one interest of the first user with one or more interests associated with a point of interest of the one or more points of interest. One or more processors provide a notification that the first user is within the first threshold distance of the point of interest.
    Type: Grant
    Filed: July 17, 2015
    Date of Patent: September 24, 2019
    Assignee: International Business Machines Corporation
    Inventors: Li-Ju Chen, Jeff H C Kuo, Chih-Wen Su, Ying-Chen Yu
  • Patent number: D874984
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: February 11, 2020
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Song-Fu Wang, Hsin-Wen Su, Hsi-Wen Chen, Chien-Chih Weng