Patents by Inventor Wen Su

Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190114242
    Abstract: A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.
    Type: Application
    Filed: October 12, 2017
    Publication date: April 18, 2019
    Inventors: Huang-Wen Su, Shi-Tsan Lin
  • Patent number: 10262944
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Grant
    Filed: December 6, 2016
    Date of Patent: April 16, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Publication number: 20190099698
    Abstract: The present disclosure discloses an impacting T-junction component regulator for regulating components of a non-azeotropic working medium, which is formed by connecting a single T-junction or a plurality of T-junctions. Each of the T-junction comprises an inlet pipe and an outlet pipe. When the impacting T-junction component regulator is formed by a plurality of connected T-junctions, the impacting T-junction component regulator further comprises an upper manifold trunk communicated with an outlet pipe of each T-junction and throttle valves located between two adjacent T-junctions. By using the characteristics of unequal vapor and liquid components of the non-azeotropic working medium and mal-distribution of two phase flows by vertical impacting T-junctions, the regulator achieves the fluid flowing through a plurality of T-junctions and throttle valves once so as to achieve the purpose of separating components.
    Type: Application
    Filed: October 27, 2016
    Publication date: April 4, 2019
    Inventors: Li ZHAO, Wen SU, Nan ZHENG, Shuai DENG, Pei LU
  • Patent number: 10236565
    Abstract: A wearable electronic device includes a device body, a wearable body, a circuit board, an antenna system and a conductive extension portion. The device body includes an upper casing and a lower casing. A feeding portion, a first grounding portion and a second grounding portion are disposed on a periphery of the circuit board. The second grounding portion is electrically connected to the upper casing. The antenna system is disposed on the inner surface of the lower casing. The feeding terminal of the antenna system is electrically connected to the feeding portion of the circuit board. The grounding terminal of the antenna system is electrically connected to the first grounding portion of the circuit board. An end of the conductive extension portion is electrically connected to the upper casing, the other end of the conductive extension portion is extended into the wearable body.
    Type: Grant
    Filed: December 1, 2017
    Date of Patent: March 19, 2019
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Yi-Ting Hsieh, Saou-Wen Su, Cheng-Tse Lee
  • Publication number: 20190081384
    Abstract: A monopole antenna is provided. The monopole antenna comprises a ground element, a radiating element, a first inductive element and a second inductive element. The radiating element includes a feed point and the feed point divides the radiating element into the first radiating portion and the second radiating portion. The second radiating portion is connected with the first radiating portion. The first radiating portion and the second radiating portion support a first frequency band and a second frequency band, respectively. The operating frequency of the first frequency band is higher than that of the second frequency band. The first inductive element is connected between the first radiating portion and the ground element. The second inductive element is connected between the second radiating portion and the ground element.
    Type: Application
    Filed: September 4, 2018
    Publication date: March 14, 2019
    Inventor: Saou-Wen Su
  • Patent number: 10199500
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: August 2, 2016
    Date of Patent: February 5, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Patent number: 10199260
    Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Hsuan-Tai Hsu, Kuan-Hsuan Ku
  • Patent number: 10177245
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: January 8, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Patent number: 10163719
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Grant
    Filed: December 15, 2015
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • Patent number: 10163644
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: December 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Patent number: 10164537
    Abstract: A switching regulator includes a first switch; a second switch coupled between the first switch and ground; an inductor coupled to a common node between the first and second switches; a capacitor coupled between the inductor and ground; a controller receiving a disable signal, and generating first and second control signals respectively for the first and second switches; and a crossing detector comparing an auxiliary voltage at the common node with a negative reference voltage to generate a comparison signal, and generating the disable signal based on the first control signal and the comparison signal. The second control signal switches into an inactive state upon the disable signal indicating a reference-crossing of the auxiliary voltage.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: December 25, 2018
    Assignee: National Taipei University of Technology
    Inventors: Ting-Wen Su, Yuh-Shyan Hwang
  • Patent number: 10158638
    Abstract: Disclosed are systems, apparatus, methods, and computer-readable storage media for providing alerts in an online social network. In some implementations, the online social network is specific to an organization having one or more internal users and one or more external users. An indication of an action associated with providing data to the online social network is received from a computing device. A group associated with the indication of the action is identified. It is determined that the identified group includes the one or more external users. Responsive to determining that the identified group includes the one or more external users, an instruction to display an alert notification is provided at the computing device.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: December 18, 2018
    Assignee: salesforce.com, inc.
    Inventors: Michael Scott Micucci, Aditya Sesha Kuruganti, Theodore James Summe, Kedar Doshi, Leonard Gestrin, Sanjaya Lai, George Wen Su
  • Publication number: 20180350993
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for weaker and softer dielectric layer. The insert layer may be applied between two weaker dielectric layers or the insert layer may be used with a single layer of dielectric material. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Application
    Filed: July 27, 2018
    Publication date: December 6, 2018
    Inventors: Yao-Jen Chang, Chih-Chien Chi, Chen-Yuan Kao, Hung-Wen Su, Kai-Shiang Kuo, Po-Cheng Shih, Jun-Yi Ruan
  • Publication number: 20180337056
    Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Rueijer Lin, Ya-Lien Lee, Chun-Chieh Lin, Hung-Wen Su
  • Publication number: 20180301789
    Abstract: The disclosure provides an antenna element. The antenna element comprises a metal substrate, a first closed slot, a feed part and a first matching part. The first closed slot is formed in the metal substrate, and comprises a first slot section and a second slot section, wherein the length of the first slot section is greater than the length of the second slot section. The feed part spans across the closed slot, the closed slot is divided into the first slot section and the second slot section by the feed part, the feed part is used for exciting the first slot section to generate a resonant mode in a first frequency band and generate a resonant mode in a second frequency band, and exciting the second slot section to generate a resonant mode in a third frequency band. The first matching part is formed on the first slot section, and is connected to parts of the metal substrate, which are positioned on two sides of the first slot section.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 18, 2018
    Inventors: Cheng-Tse Lee, Saou-Wen Su
  • Publication number: 20180294111
    Abstract: The invention discloses a keyboard switch including a base, a cover covering the base to form a cavity, an upper guide core disposed in the cavity and an upper guide core limiting mechanism including a lower guide core elastomer, a lower guide core, a middle guide core spring and a middle guide core sequentially disposed on the base. The upper guide core and the middle guide core are connected through an upper guide core spring. The keyboard switch of the invention provides accuracy of the press-conduction displacement, accurate positioning of the conduction course, and adjustability of the press force, such that the press force becomes more balanced, and the keyboard switch is conducted when the guide core is pressed downwards. Thus, the overall press stability of the keyboard switch is improved.
    Type: Application
    Filed: April 2, 2018
    Publication date: October 11, 2018
    Inventors: Chih-Wen SU, Yuang-Feng HU
  • Publication number: 20180267629
    Abstract: The invention provides a scroll wheel module, which includes an adjustment wheel, a scroll wheel and a transmission mechanism. The adjustment wheel includes an adjustment portion. The scroll wheel includes a contact portion. The transmission mechanism has a first end and a second end opposite to each other, the first end is connected to the adjustment portion of the adjustment wheel, and the second end is adjacent to the scroll wheel. When the adjustment wheel is rotated, the first end of the transmission mechanism produces a displacement relative to the adjustment portion such that the second end of the transmission mechanism applies a force to the contact. A magnitude of the force is proportional to a rotational force of the scroll wheel.
    Type: Application
    Filed: January 15, 2018
    Publication date: September 20, 2018
    Applicants: LITE-ON ELECTRONICS (GUANGZHOU) LIMITED, Lite-On Technology Corporation
    Inventors: Chin-Yuan Lin, Chih-Wen Su, Hong-Che Yen, Urey Deng
  • Patent number: 10050116
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Ya-Lien Lee, Yen-Shou Kao
  • Patent number: 10043882
    Abstract: A method of forming a semiconductor device includes the following steps. A substrate is provided, and the substrate has a first region. A barrier layer is then formed on the first region of the substrate. A first work function layer is formed on the barrier layer. An upper half portion of the first work function layer is converted into a non-volatile material layer. The non-volatile material layer is removed and a lower half portion of the first work function layer is kept.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: August 7, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Zhen Wu, Hsiao-Pang Chou, Chiu-Hsien Yeh, Shui-Yen Lu, Jian-Wei Chen
  • Patent number: D828310
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: September 11, 2018
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang