Abstract: The present disclosure provides a loop antenna, including a substrate, and a grounding portion, a radiating portion, a matching portion, and a feeding portion that are located on the substrate. The grounding portion includes a first grounding segment and a second grounding segment. The second grounding segment is perpendicular to the first grounding segment, and a first end of the second grounding segment is connected to a first end of the first grounding segment. The radiating portion includes a first radiating segment and a second radiating segment. The first radiating segment is connected to a second end of the first grounding segment and extending from the first grounding segment towards a direction away from the first grounding segment. The second radiating segment is connected to the first radiating segment and extending from the first radiating segment towards a direction facing the second grounding segment.

Abstract: A sensing circuit for metal object includes a resonating element, a power supply circuit, and a determining circuit. The resonant element is coupled to the power supply circuit and the determining circuit. The power supply circuit drives the resonating element to generate an oscillation, and the determining circuit determines the position of the metal object relative to the resonating element according to the energy change of the resonating element.

Abstract: A universal serial bus (USB) testing method includes selecting a selected test mode from test modes, creating a USB communication link between a USB device and a testing fixture board, generating, by the testing fixture board, a test-triggering instruction corresponding to the selected test mode according to the selected test mode, sending the test-triggering instruction to the USB device with the USB communication link, generating, by the USB device, a testing packet corresponding to the selected test mode according to the test-triggering instruction, and outputting the testing packet repeatedly from at least one external port of the USB device.

Abstract: A method includes forming a trench in a low-K dielectric layer, where the trench exposes an underlying contact area of a substrate. A first tantalum nitride (TaN) layer is conformally deposited within the trench, where the first TaN layer is deposited using atomic layer deposition (ALD) or chemical vapor deposition (CVD). A tantalum (Ta) layer is deposited on the first TaN layer conformally within the trench, where the Ta layer is deposited using physical vapor deposition (PVD). An electroplating process is performed to deposit a conductive layer over the Ta layer. A via is formed over the conductive layer, where forming the via includes depositing a second TaN layer within the via and in contact with the conductive layer.

Abstract: The invention discloses a keyboard switch including a base, a cover covering the base to form a cavity, an upper guide core disposed in the cavity and an upper guide core limiting mechanism including a lower guide core elastomer, a lower guide core, a middle guide core spring and a middle guide core sequentially disposed on the base. The upper guide core and the middle guide core are connected through an upper guide core spring. The keyboard switch of the invention provides accuracy of the press-conduction displacement, accurate positioning of the conduction course, and adjustability of the press force, such that the press force becomes more balanced, and the keyboard switch is conducted when the guide core is pressed downwards. Thus, the overall press stability of the keyboard switch is improved.

Abstract: This disclosure provides a loop antenna, including a substrate, and a grounding portion, a matching portion, a first radiating portion, a second radiating portion, and a feed portion that are located on the substrate. The first radiating portion includes a first radiating segment and a second radiating segment. The grounding portion includes a first grounding segment and a second grounding segment. The second grounding segment is perpendicularly connected to a first end of the first grounding segment. The matching portion is connected to a second end of the first grounding segment and the first radiating segment. The first radiating segment extends from the matching portion away from the first grounding segment. The second radiating segment extends from the first radiating segment toward the second grounding segment. There is a coupling gap between the second radiating portion and the second radiating segment, and the second radiating portion extends toward the second grounding segment.

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

Abstract: The present disclosure relates to structures and associated systems for connecting a hub apparatus to a wheel. In some embodiments, the hub apparatus includes (1) a housing assembly having an outer radius; and (2) a mounting portion circumferentially provided on at least one side surface of the housing assembly. The mounting portion is formed with a plurality of coupling structures configured to couple the hub apparatus to a wheel rim. The mounting portion defines a first radius smaller than the outer radius.

Abstract: A semiconductor device and method of manufacture are provided which utilize an air gap to help isolate conductive structures within a dielectric layer. A first etch stop layer is deposited over the conductive structures, and the first etch stop layer is patterned to expose corner portions of the conductive structures. A portion of the dielectric layer is removed to form an opening. A second etch stop layer is deposited to line the opening, wherein the second etch stop layer forms a stepped structure over the corner portions of the conductive structures. Dielectric material is then deposited into the opening such that an air gap is formed to isolate the conductive structures.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a conductive plug over a substrate; a conductive feature over the conductive plug, wherein the conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a bottom surface; and a carbon-containing barrier layer having a first portion along the first sidewall of the conductive feature, a second portion along the second sidewall of the conductive feature, and a third portion along the bottom surface of the conductive feature.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process.

Abstract: The present disclosure provides methods for forming a conductive fill material (e.g., a conductive feature) by a physical vapor deposition (PVD) process. In one embodiment, a method of forming a conductive fill material on a substrate includes maintaining a first substrate temperature at a first range for a first period of time while forming a pre-layer of a conductive fill material on a substrate, providing a thermal energy to the substrate to maintain the substrate at a second substrate temperature at a second range for a second period of time, wherein the second substrate temperature is higher than the first substrate temperature, and continuously providing the thermal energy to the substrate to maintain the substrate a third substrate temperature at a third range for a third period of time to form a bulk layer of the conductive fill material on the substrate.

Abstract: Embodiments disclosed herein relate generally to capping processes and structures formed thereby. In an embodiment, a conductive feature, formed in a dielectric layer, has a metallic surface, and the dielectric layer has a dielectric surface. The dielectric surface is modified to be hydrophobic by performing a surface modification treatment. After modifying the dielectric surface, a capping layer is formed on the metallic surface by performing a selective deposition process. In another embodiment, a surface of a gate structure is exposed through a dielectric layer. A capping layer is formed on the surface of the gate structure by performing a selective deposition process.

Abstract: A fabricating method of a semiconductor structure includes the following steps. A gate material layer is formed on a semiconductor substrate. A patterned mask layer is formed on the gate material layer. The pattern mask layer includes at least one opening exposing a part of the gate material layer. An impurity treatment is performed to the gate material layer partially covered by the pattern mask layer for forming at least one doped region in the gate material layer. An etching process is performed to remove the gate material layer including the doped region. A dummy gate may be formed by patterning the gate material layer, and the impurity treatment may be performed after the step of forming the dummy gate. The performance of the etching processes for removing the gate material layer and/or the dummy gate may be enhanced, and the gate material residue issue may be solved accordingly.

Abstract: A device comprises a semiconductor substrate; a dielectric layer deposited over the semiconductor substrate, the dielectric layer including a trench; and a structure in the trench. The structure includes a chemical vapor deposition (CVD) TaN layer formed on a side wall of the trench; a physical vapor deposition (PVD) Ta layer formed over the CVD TaN layer; and a metal-containing layer formed over the PVD Ta layer.

Abstract: A method of fabricating a contact hole structure includes providing a substrate with an epitaxial layer embedded therein. Next, an interlayer dielectric is formed to cover the substrate. After that, a first hole is formed in the interlayer dielectric and the epitaxial layer. Later, a mask layer is formed to cover a sidewall of the first hole and expose a bottom of the first hole. Subsequently, a second hole is formed by etching the epitaxial layer at the bottom of the first hole and taking the mask layer and the interlayer dielectric as a mask, wherein the first hole and the second hole form a contact hole. Then, the mask layer is removed. Finally, a silicide layer is formed to cover the contact hole.

Abstract: A sensing circuit for metal object includes a resonating element, a power supply circuit, and a determining circuit. The resonant element is coupled to the power supply circuit and the determining circuit. The power supply circuit drives the resonating element to generate an oscillation, and the determining circuit determines the position of the metal object relative to the resonating element according to the energy change of the resonating element.