Patents by Inventor Wen Su

Wen Su has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9754882
    Abstract: A representative semiconductor device includes a first dielectric layer overlying a substrate, at least a first opening in the first dielectric layer, a conformal dense layer lining the at least first opening in the first dielectric layer, a barrier layer overlying the conformal dense layer, a conductive feature in the at least first opening, where a portion of the first dielectric layer between any two adjacent conductive features is removed to form a second opening, the second opening exposing the conformal dense layer between the two adjacent conductive features, and a second dielectric layer having an air gap formed therein, the second dielectric layer disposed between the two adjacent conductive features.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: September 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chien Chi, Hung-Wen Su
  • Patent number: 9755057
    Abstract: A method of fabricating a semiconductor device is disclosed. A substrate is provided. A dummy gate stack is formed on the substrate. The dummy gate stack includes a gate dielectric layer and an amorphous silicon dummy gate on the gate dielectric layer. The amorphous silicon dummy gate is transformed into a nano-crystalline silicon dummy gate. A spacer is formed on a sidewall of the nano-crystalline silicon dummy gate. A source/drain region is formed in the substrate on either side of the dummy gate stack.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: September 5, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Po-Wen Su, Shui-Yen Lu
  • Patent number: 9747250
    Abstract: A system for improving memory management in a hybrid programming environment where a server program receives a request to execute a script. The server program instructs an embedded script engine to execute the script. The server program creates a session manager to manage objects associated with the script. The objects are comprised of host objects that reside in a program memory space, and script objects that reside in an embedded script engine memory space. The session manager creates a session associated with the execution of the script, and associated objects created during the execution of the script. Upon receiving notification of completion and/or termination of the execution of the script, the server program requests invalidation and/or deletion of the objects associated with the session. Deletion of host objects immediately releases memory in the program memory space without waiting for the scheduled garbage collection.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: August 29, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Tony Ffrench, Libra C. Huang, Mei-Jiuang Juang, Timothy J. Smith, Chih-Wen Su, Yi-hong Wang
  • Patent number: 9722303
    Abstract: A wearable electronic device includes a body and a wearing element. The body includes a conductive frame. The conductive frame includes a feeding point and at least one grounding point to form a first current path and a second current path. Furthermore, the conductive frame forms a loop antenna via the first current path and the second current path, respectively, so as to operate in a first band and a second band. The wearing element is connected to the body.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 1, 2017
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Yi-Ting Hsieh, Saou-Wen Su, Chih-Chung Lin
  • Patent number: 9711368
    Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.
    Type: Grant
    Filed: April 15, 2013
    Date of Patent: July 18, 2017
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Lung-En Kuo, Po-Wen Su, Chen-Yi Weng, Hsuan-Hsu Chen
  • Publication number: 20170200800
    Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a gate stack, a spacer layer, and a dielectric layer over a substrate. The method includes removing a first portion of the dielectric layer to form a first hole in the dielectric layer. A second portion of the dielectric layer is under the first hole. The method includes forming a first protection layer over the gate stack and the spacer layer. The method includes forming a second protection layer over the first protection layer. The second protection layer includes a metal compound material, and the first protection layer and the second protection layer includes a same metal element. The method includes removing the second portion of the dielectric layer to form a through hole. The method includes forming a conductive contact structure in the through hole.
    Type: Application
    Filed: January 7, 2016
    Publication date: July 13, 2017
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Ping LIU, Hung-Chang HSU, Hung-Wen SU, Ming-Hsing TSAI, Rueijer LIN, Sheng-Hsuan LIN, Ya-Lien LEE, Yen-Shou KAO
  • Publication number: 20170170329
    Abstract: In one embodiment, a flexible device is provided. The flexible device may include a flexible substrate, a buffer layer, a light reflective layer, and a device layer. The buffer layer is located on the flexible substrate. The light reflective layer is located on the flexible substrate, wherein the light reflective layer has a reflection wavelength of 200 nm˜1100 nm, a reflection ratio of greater than 80%, and a stress direction of the light reflective layer is the same as a stress direction of the flexible substrate. The device layer is located on the light reflective layer and the buffer layer.
    Type: Application
    Filed: March 7, 2016
    Publication date: June 15, 2017
    Inventors: Ching-Wen Su, Tai-Jui Wang, Hsiao-Chiang Yao, Tsu-Chiang Chang, Bo-Yuan Su
  • Publication number: 20170170543
    Abstract: An antenna is provided. The antenna includes: an antenna ground plane; a radiating unit parallel to the antenna ground plane, the radiating unit including: a common unit; a first branch extended from the common unit along a first direction; a second branch extended from the common unit along a second direction, wherein the first direction and the second direction are inverse; a third branch separated from the first branch and the second branch and extending outwardly from the common unit; a shorting unit located between a plane of radiating unit located and a plane of the antenna ground plane and connected to the common unit and the antenna ground plane; and a feeding unit located between a plane of the radiating unit and a plane of the antenna ground plane, wherein the feeding unit is separated from the shorting unit and connected to the third branch, and the shorting unit and the feeding unit are located on the same side.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 15, 2017
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Cheng-Tse Lee, Saou-Wen Su
  • Publication number: 20170170292
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a first gate stack over a substrate. The first gate stack includes a gate electrode, a first hard mask (HM) disposed over the gate electrode, and sidewall spacers along sidewalls of the first gate stack. The method also includes forming a first dielectric layer over the first gate stack, forming a second HM over the first HM and top surfaces of sidewall spacers, forming a second dielectric layer over the second HM and the first dielectric layer and removing the second and first dielectric layers to form a trench to expose a portion of the substrate while the second HM is disposed over the first gate stack.
    Type: Application
    Filed: December 15, 2015
    Publication date: June 15, 2017
    Inventors: Hsiao-Ping Liu, Hung-Chang Hsu, Hung-Wen Su, Ming-Hsing Tsai, Rueijer Lin, Sheng-Hsuan Lin, Syun-Ming Jang, Ya-Lien Lee, Yen-Shou Kao
  • Patent number: 9672352
    Abstract: Embodiments relate to an isolated program execution environment. An aspect includes receiving, by the isolated program execution environment on a computer comprising a processor and a memory, a request to run a program. Another aspect includes wrapping program code corresponding to the program as a function. Another aspect includes cloning a real global object of the isolated program execution environment to create a fake global object. Another aspect includes passing the fake global object to the function. Another aspect includes executing the function, such that the function executes the program.
    Type: Grant
    Filed: November 11, 2016
    Date of Patent: June 6, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony Ffrench, Libra C. Huang, Timothy J. Smith, Chih-Wen Su, Yi-Hong Wang
  • Publication number: 20170133324
    Abstract: A semiconductor structure with an improved metal structure is described. The semiconductor structure can include a substrate having an upper surface, an interconnect layer over the upper surface, and an additional structure deposited over the interconnect layer. The interconnect layer can include a patterned seed layer over the substrate, at least two metal lines over the seed layer, and a dielectric material between adjacent metal lines. A barrier layer can be deposited over the at least two metal lines. Methods of making the semiconductor structures are also described.
    Type: Application
    Filed: January 9, 2017
    Publication date: May 11, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wen-Jiun LIU, Chen-Yuan KAO, Hung-Wen SU, Ming-Hsing TSAI, Syun-Ming JANG
  • Patent number: 9632498
    Abstract: A computer-implemented system and method of compensating for filling material losses in a semiconductor process. The computer-implemented method includes determining using a computer a pattern density difference between a first circuit pattern above a semiconductor substrate and a second circuit pattern adjacent to the first pattern. A dummy pattern is inserted between the first pattern and the second pattern so as to compensate for an estimated loss of filling material induced during electrochemical plating by the pattern density difference exceeding a threshold pattern density difference.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Yi Chang, Liang-Yueh Ou Yang, Chen-Yuan Kao, Hung-Wen Su
  • Patent number: 9627746
    Abstract: A wireless communication apparatus and an antenna system therein are provided. The antenna system includes a grounding portion and an antenna body. The grounding portion includes a ground plane and a conducting element. The conducting element is perpendicular to the ground plane and is connected to the ground plane to provide a first current path. The antenna body includes a main radiating portion and a short circuit portion. The main radiating portion is parallel to the ground plane and provides a second current path. An end of the main radiating portion is electrically connected to a signal source. The short circuit portion is electrically connected between the main radiating portion and the conducting element and provides a third current path. The directions of the first current path, the second current path and the third current path are perpendicular mutually.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: April 18, 2017
    Assignee: ASUSTeK COMPUTER INC.
    Inventors: Saou-Wen Su, Fang-Hsien Chu, Chih-Chung Lin
  • Publication number: 20170084485
    Abstract: An interconnect layer is disposed over a substrate. The interconnect layer includes a plurality of dielectric segments interleaved with a plurality of metal components. A plurality of vias is disposed below, and electrically coupled to, a first group of the metal components. A plurality of dielectric components is disposed underneath a second group of the metal components. The dielectric components interleave with the vias. A conductive liner is disposed below a bottom surface and on sidewalk of the vias. A dielectric barrier layer is disposed below a bottom surface and on sidewalls of the dielectric segments. The dielectric barrier layer and the dielectric segments have different material compositions.
    Type: Application
    Filed: December 6, 2016
    Publication date: March 23, 2017
    Inventors: Chun-Chieh Lin, Hung-Wen Su, Ming-Hsing Tsai, Syun-Ming Jang
  • Publication number: 20170081775
    Abstract: A method of plating a metal layer on a work piece includes exposing a surface of the work piece to a plating solution, and supplying a first voltage at a negative end of a power supply source to an edge portion of the work piece. A second voltage is supplied to an inner portion of the work piece, wherein the inner portion is closer to a center of the work piece than the edge portion. A positive end of the power supply source is connected to a metal plate, wherein the metal plate and the work piece are spaced apart from each other by, and are in contact with, the plating solution.
    Type: Application
    Filed: December 1, 2016
    Publication date: March 23, 2017
    Inventors: Chen-Yuan Kao, Hung-Wen Su, Minghsing Tsai
  • Publication number: 20170083111
    Abstract: An optical mouse is provided with a conversion unit, a control unit, an optical sensing unit, a light emitting unit, and a switch unit. The conversion unit is electrically connected to a working voltage source, the control unit, and the optical sensing unit. The conversion unit is configured to convert voltage to supply power to the control unit, the optical sensing unit, and the light emitting unit. The control unit is electrically connected to the optical sensing unit. The switch unit is electrically connected to the light unit. When the switch unit is in a turn-off state, the light emitting unit stops emitting light toward a trace surface. The optical sensing unit senses a darkness and transfers darkness data to the control unit. The control unit performs a configured function based on the darkness data.
    Type: Application
    Filed: June 20, 2016
    Publication date: March 23, 2017
    Inventors: CHIN-FA WU, YAO-CHIH YANG, ER-HAO CHEN, CHIH-WEN SU, CHEN-YU TSAI
  • Patent number: 9600387
    Abstract: Providing efficient data replication for a transaction processing server is provided. A notification is received from the transaction processing server which completes a transaction of a message. The notification includes a message digest and a message identifier. The message identifier in the received notification is compared with a stored message identifier. In response to a match of the comparing of the message identifier, the message digest in the received notification is compared with a stored message digest. In response to a match of the comparing of the message digest, a stored input message is directly stored in a physical storage.
    Type: Grant
    Filed: March 26, 2014
    Date of Patent: March 21, 2017
    Assignee: International Business Machines Corporation
    Inventors: Johnson Y S Chiang, Jeffrey C H Liu, Chih-Wen Su, Ying-Kai Wang
  • Patent number: D784788
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: April 25, 2017
    Assignee: Gogoro Inc.
    Inventors: Chien-Chih Weng, Hsin-Wen Su
  • Patent number: D789883
    Type: Grant
    Filed: September 4, 2014
    Date of Patent: June 20, 2017
    Assignee: GOGORO INC.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang
  • Patent number: D794510
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: August 15, 2017
    Assignee: Gogoro Inc.
    Inventors: Hok-Sum Horace Luke, Chien-Chih Weng, Hsin-Wen Su, Song-Fu Wang, Chi-Wang Lien