Abstract: A vehicle transmission includes a first rotating element, second rotating element, first retainer ring, and second retainer ring. The first rotating element has an exterior surface that defines a first ring groove. The second rotating element is configured to limit movement of friction plates during clutch engagement. The second rotating element is disposed about the exterior surface and has an interior surface that defines a second ring groove. The first retainer ring is disposed in the first ring groove. The second retainer ring is disposed in the second ring groove and thereby restricts movement of the first retainer ring in a radially outward direction.

Abstract: An electronic device includes a first body, a second body and at least one driving mechanism. The second body includes a casing and a flexible screen installed on the casing. The driving mechanism includes a shaft, a driving element and a linking assembly. The shaft has first and second connecting portions opposite to each other, the first connecting portion is fixed to the first body, and the second body is pivoted to the second connecting portion. The driving element is sleeved on the shaft and is located in the casing. The linking assembly is carried by the casing and covered by the flexible screen. When the second body is folded onto the first body, the flexible screen keeps flat. When the second body is unfolded with respect to the first body, the driving element is rotated and moved with respect to the shaft to drive the linking assembly to move, and the linking assembly drives the flexible screen to bend.

Abstract: The invention provides an electronic device, a hinge assembly, and an AR interaction process for an electronic device. The electronic device includes a first body, a second body, a hinge assembly, and a rotatable lens. The hinge assembly includes a first hinge, a second hinge, a third hinge, and an L-shaped hinge. The L-shaped hinge has a first segment and a second segment. The first segment is pivotally connected to the first body through the first hinge, the second segment is pivotally connected to the second body through the second hinge, and the first hinge, the second hinge, and the third hinge are parallel to each other and are not coaxial with each other. In addition, the rotatable lens is assembled to the second segment.

Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.

Abstract: A method for manufacturing a semiconductor device package includes: (1) providing a first encapsulation layer; (2) disposing an adhesive layer on the first encapsulation layer; (3) disposing a first die on the adhesive layer; and (4) forming a second encapsulation layer covering the first die, the adhesive layer, and the first encapsulation layer.

Abstract: According to one or more embodiments, a clutch pack includes a first set of clutch plates arranged in an alternating configuration with a second set of clutch plates. The first set of clutch plates has a plurality of friction pads made of friction material and defining channels in the friction material. The channels are configured to allow lubricant to flow between the friction pads. Each of the friction pads defines a groove in the friction pad. The groove is disconnected from the channels. The groove thereby creates a flow induced high pressure region forcing the first set of clutch plates to a center between the second set of clutch plates.

Abstract: Disclosed are an image tuning device and an image tuning method. The image tuning method includes the following steps: dividing an image area into a plurality of blocks for executing brightness adjustment individually, in which the blocks include a target block and at least one neighboring block; receiving pixel data of the target block to calculate a target block brightness value; receiving pixel data of the at least one neighboring block to calculate at least one neighboring block brightness value; calculating a calculated brightness value of a target pixel within the target block according to the target block brightness value and the at least one neighboring block brightness value; and generating an adjusted brightness value of the target pixel by adjusting an original brightness value of the target pixel according to the calculated brightness value.

Abstract: The present invention provides a packaging unit for liquid sample loading devices applied in an electron microscope. The liquid sample loading devices may be easily, rapidly, precisely and stably aligned and packaged by an engagement of an upper jig and a bottom jig as well as a first fixing pillar supported in a slide track of the packaging unit. Accordingly, efficiency and a yield of packaging the liquid sample loading devices may be improved. In addition, the packaging unit for the liquid sample loading devices of the present invention may directly package a liquid sample, and thus the liquid sample may maintain its original state.

Abstract: A liquid sample carrier includes a first base that includes a first carrying portion having a first sample holding surface, and a second base that is connectable to the first base and that includes a second carrying portion, a support layer, and a second sample holding surface. The second carrying portion is stackable on the first carrying portion, and has a surrounding wall defining a through hole. The support layer is connected to the second carrying portion and has a window area corresponding to the through hole, and a peripheral area surrounding the window area. The second sample holding surface is connected to the support layer. A sample receiving area is formed between the first and second sample holding surfaces.

Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.

Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a first metal layer, a substrate, an epitaxy layer, a plurality of first trench wells, a plurality of second trench wells, a plurality of body structure layers, a plurality of polysilicon layers, and a second metal layer. A part of a depletion region is formed between each first trench well and the epitaxy layer and between a body structure layer corresponding to the each first trench well and the epitaxy layer, and a rest part of the depletion region is formed between a second trench well corresponding to the each first trench well and the epitaxy layer. The plurality of second trench wells increase a breakdown voltage of the power MOSFET device and reduce a conduction resistor of the power MOSFET device.

Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.