Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.

Abstract: A micro electro mechanical system (MEMS) includes a circuit substrate, a first MEMS structure disposed over the circuit substrate, and a second MEMS structure disposed over the first MEMS structure.

Abstract: A semiconductor package includes a multilayer substrate, a device die, an insulating encapsulant, and a shielding structure. The multilayer substrate has a first surface and a second surface opposite to the first surface. The multilayer substrate includes through holes, and each of the through holes extends from the first surface to the second surface. The device die is disposed on the first surface of the multilayer substrate. The insulating encapsulant is disposed on the first surface of the multilayered substrate and encapsulating the device die. The shielding structure is disposed over the first surface of the multilayer substrate. The shielding structure includes a cover body and conductive pillars. The cover body covers the device die and the insulating encapsulant. The conductive pillars are connected to the cover body and fitted into the through holes of the multilayer substrate.

Abstract: An inductive device includes an insulating layer, a lower magnetic layer, and an upper magnetic layer that are formed such that the insulating layer does not separate the lower magnetic layer and the upper magnetic layer at the outer edges or wings of the inductive device. The lower magnetic layer and the upper magnetic layer form a continuous magnetic layer around the insulating layer and the conductors of the inductive device. Magnetic leakage paths are provided by forming openings through the upper magnetic layer. The openings may be formed through the upper magnetic layer by semiconductor processes that have relatively higher precision and accuracy compared to semiconductor processes for forming the insulating layer such as spin coating. This reduces magnetic leakage path variation within the inductive device and from inductive device to inductive device.

Abstract: A method for video quality detection and an image processing circuit thereof are provided. In the method, an image-processing circuit receives video signals with at least one frame image, and obtains brightness information of pixels from the frame image. A threshold is applied to the pixels of each frame in order to screen the brightness features that can be regarded as an attribute of each frame image. Therefore, a brightness distribution feature with respect to the pixels of each frame image can be obtained by a statistic method. Statistics showing the brightness distribution can be used to determine a quality of each frame image or a video. The image processing circuit can accordingly select an image processing process corresponding to the image quality of each frame image or the whole video.

Abstract: A flexible display includes a bottom plate, a support plate, two hinge modules, a frame body, a bending module and a flexible panel. The support plate is provided with a first end and a second end. The first end is rotatably connected to the bottom plate. The hinge modules are disposed at the second end of the support plate. The frame body is provided with a fixed frame and a plurality of turning frames. The fixed frame is connected to the hinge modules. The plurality of turning frames are pivoted to two opposite sides of the fixed frame respectively. The bending module is connected with the fixed frame and the plurality of turning frames. The flexible panel is disposed on the frame body and covers the bending module. When the flexible display is switched to a touch mode, the bending module drives the plurality of turning frames to be flush with the fixed frame so that the flexible panel is in a flat plate shape.

Abstract: A method for processing a static pattern in an image and a circuit system are provided. In the method, each of frames of a video is divided into multiple areas. Several algorithms are used to calculate a static pattern index of every area. The static pattern index is used as a reference for determining if the area covers part or entire of a static pattern. An index threshold can be used to check the areas that are determined as the static pattern initially. A time threshold is then used to confirm the areas with the static pattern in every frame. Image data of the areas which are determined as the static patterns can then be adjusted, such as having brightness of the area that is determined as part or entire of the static patterns decreased, for preventing the display panel from negative effects of the static pattern.

Abstract: A network system comprising: a control node; a first head node, comprising a first head forward port, a first head backward port and a first head backup port, wherein the first head forward port is connected to the control node; a first ordinary node, comprising a first forward port, a first backward port and a first backup port, wherein the first forward port is connected to the first head backward port; a second ordinary node, comprising a second forward port, a second backward port and a second backup port, wherein the second forward port is connected to the first backward port; and a third ordinary node, comprising a third forward port, a third backward port and a third backup port, wherein the third forward port is connected to the second backward port, wherein the third backup port is connected to the first head backup port.

Abstract: A multi-functional notebook includes a first body, a processing unit, a second body, and two joysticks. The first body has two accommodating spaces and a first wireless module. The processing unit is disposed in the first body and coupled to the first wireless module, and serves as a control core. The second body is connected to the first body and has a display unit coupled to the processing unit. The two joysticks are detachably disposed in the two accommodating spaces respectively and are coupled to the processing unit. Each of the joysticks has a second wireless module, and the two second wireless modules are coupled to the first wireless module for signal transmission. The processing unit is adapted to detect a connection state between each of the joysticks and the first body to switch to a corresponding operation mode.

Abstract: A method for detecting defects in a semiconductor device including singulating a die having a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the die and the detecting devices. The method further includes probing the first probe pad and the second probe pad to determine a connection status of the detecting device, and recognizing a defect when the connection status of the detecting device indicates an open circuit.

Abstract: A touch device has multiple charging traces distributed under the touch operation area. When the object hovers over or contacts the touch operation area, the control unit of the touch device obtains the corresponding position of the object through the sensing signal of the electrode units. The control unit in turn connect the charging traces adjacent to the corresponding position of the object to form at least one charging loop. In the process of the touch operation on the touch device, the object can be charged at the same time, and the convenience of use can be improved.

Abstract: A semiconductor device includes a magnetic random access memory (MRAM). The MRAM comprises a plurality of MRAM cells including a first type MRAM cell and a second type MRAM cell. Each of the plurality of MRAM cells includes a magnetic tunneling junction (MTJ) layer including a pinned magnetic layer, a tunneling barrier layer and a free magnetic layer. A size of the MTJ film stack of the first type MRAM cell is different from a size of the MTJ film stack of the second type MRAM cell. In one or more of the foregoing and following embodiments, a width of the MTJ film stack of the first type MRAM cell is different from a width of the MTJ film stack of the second type MRAM cell.

Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.

Abstract: A semiconductor package structure includes a wiring structure, a semiconductor module, a protection layer and a plurality of outer conductive vias. The wiring structure includes at least one dielectric layer and at least one redistribution layer. The semiconductor module is electrically connected to the wiring structure. The semiconductor module has a first surface, a second surface opposite to the first surface and a lateral surface extending between the first surface and the second surface. The protection layer covers the lateral surface of the semiconductor module and a surface of the wiring structure. The outer conductive vias surround the lateral surface of the semiconductor module, electrically connect to the wiring structure, and extend through a dielectric layer of the wiring structure and the protection layer.

Abstract: A hollow polymeric fiber includes: a tetragonal shape sectional area having four corner points and four edges. The four corner points form a square. All four edges are concave or straight. The fiber has a cross sectional area hollowness ranging from 12 to 25%. The fiber has a titer in a range of from 4 to 16 dtex.