Patents by Inventor Wen Tseng

Wen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10720214
    Abstract: A memory unit includes a substrate and a floating gate memory cell. The floating gate memory cell includes an erase gate structure disposed on the substrate, floating gate structures select gates, a common source and drains. The common source is disposed in the substrate, and the erase gate structure is disposed on the common source. The floating gate structures protrude from recesses of the substrate at two opposite sides of the erase gate structure. A method for controlling the memory unit includes applying an erase gate programming voltage on the erase gate structure, applying a control gate programming voltage on the common source, applying a bit line programming voltage on the drains, and applying word line programming voltage on the select gates, in which the control gate programming voltage is greater than the erase gate programming voltage.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: July 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20200206607
    Abstract: A multi-functional notebook includes a first body, a processing unit, a second body, and two joysticks. The first body has two accommodating spaces and a first wireless module. The processing unit is disposed in the first body and coupled to the first wireless module, and serves as a control core. The second body is connected to the first body and has a display unit coupled to the processing unit. The two joysticks are detachably disposed in the two accommodating spaces respectively and are coupled to the processing unit. Each of the joysticks has a second wireless module, and the two second wireless modules are coupled to the first wireless module for signal transmission. The processing unit is adapted to detect a connection state between each of the joysticks and the first body to switch to a corresponding operation mode.
    Type: Application
    Filed: December 27, 2019
    Publication date: July 2, 2020
    Applicant: COMPAL ELECTRONICS, INC.
    Inventors: Hsiao-Wen Tseng, Jyh-Chyang Tzou, Yi-Hsun Liu, Yao-Hsien Yang
  • Patent number: 10699977
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Grant
    Filed: July 8, 2019
    Date of Patent: June 30, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Patent number: 10685852
    Abstract: A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: June 16, 2020
    Assignee: NATIONAL CHENG KUNG UNIVERSITY
    Inventors: Po-Tsung Hsieh, Chia-Ming Yang, In-Gann Chen, Shih-Wen Tseng, Ya-Wen Tsai, Ya-Wen Chuang
  • Patent number: 10679980
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tseng Chin Lo, Molly Chang, Ya-Wen Tseng, Chih-Ting Sun, Zi-Kuan Li, Bo-Sen Chang, Geng-He Lin
  • Patent number: 10665602
    Abstract: A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.
    Type: Grant
    Filed: November 21, 2018
    Date of Patent: May 26, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yun-Chi Wu, Yu-Wen Tseng
  • Publication number: 20200144078
    Abstract: A chip packaging device is provided, which includes a main body unit, packaging unit and an aligning unit. The main body unit includes a mounting base, holder and a rotational platform. The packaging unit includes upper and lower bonding elements, upper and lower chips and a mask; a vertical axis is at the middle of the upper and the lower bonding elements, and a horizontal axis is above the lower bonding element. The aligning unit includes an aligning detector and a first focusing detector. When the lower chip and the mask are disposed on the lower bonding element, place the liquid sample in the mask and spread a packaging adhesive over the surface thereof; then, remove the mask and use the aligning detector and the first focusing detector to detect the position of the lower chip respectively, such that the chips can be aligned and bonded with each other.
    Type: Application
    Filed: November 26, 2018
    Publication date: May 7, 2020
    Inventors: Po-Tsung Hsieh, Chia-Ming Yang, In-Gann Chen, Shih-Wen Tseng, Ya-Wen Tsai, Ya-Wen Chuang
  • Publication number: 20200135613
    Abstract: A method includes forming a solder layer on a surface of one or more chips. A lid is positioned over the solder layer on each of the one or more chips. Heat and pressure are applied to melt the solder layer and attach each lid to a corresponding solder layer. The solder layer has a thermal conductivity of ?50 W/mK.
    Type: Application
    Filed: October 28, 2019
    Publication date: April 30, 2020
    Inventors: Yang-Che CHEN, Chen-Hua LIN, Huang-Wen TSENG, Victor Chiang LIANG, Chwen-Ming LIU
  • Publication number: 20200133457
    Abstract: A touch system includes a touch device and an input device. The uplink signal transmitted by the touch device includes a timestamp. The input device transmits a downlink signal through the electrode unit and transmits a side information through a wireless communication unit. The inclusion of the corresponding timestamp in the side information ensures that the side information is combined with the corresponding downlink signal to correctly present the user's operation.
    Type: Application
    Filed: September 5, 2019
    Publication date: April 30, 2020
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Han-Wei Chen, Hsuan-Wen Tseng, Yi-Hsin Tao, Chia-Hsing Lin
  • Publication number: 20200133428
    Abstract: A touch device has multiple charging traces distributed under the touch operation area. When the object hovers over or contacts the touch operation area, the control unit of the touch device obtains the corresponding position of the object through the sensing signal of the electrode units. The control unit in turn connect the charging traces adjacent to the corresponding position of the object to form at least one charging loop. In the process of the touch operation on the touch device, the object can be charged at the same time, and the convenience of use can be improved.
    Type: Application
    Filed: October 14, 2019
    Publication date: April 30, 2020
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: HAN-WEI CHEN, HSUAN-WEN TSENG, YI-HSIN TAO, CHIA-HSING LIN
  • Publication number: 20200133436
    Abstract: A touch system has a touch device and an input device. The touch system executes a first mode and a second mode at different times. In the first mode, the touch device transmits a modulation signal to drive the touch electrodes and to be used as an uplink signal. The input device receives the modulation signal. In the second mode, the touch device receives the downlink signal from the input device. Thus, the touch device does not have to transmit the driving signal and the uplink signal at different times. Then the time is saved for the rest work periods so that every work periods get longer length of time.
    Type: Application
    Filed: October 17, 2019
    Publication date: April 30, 2020
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: HAN-WEI CHEN, HSUAN-WEN TSENG, YI-HSIN TAO, CHIA-HSING LIN, CHEN-YU HOU, CHIEH-WEN CHEN
  • Patent number: 10632081
    Abstract: Disclosed is an intralymphatic delivery method for treating lymphatic cancer using hyaluronan nanoparticles. These nanoparticles include a hyaluronic acid derivative and a platinum compound. The hyaluronan derivative includes hyaluronic acid, modified histidine and optionally one or more of a polymer or a C4-C20 alkyl. The hyaluronic acid derivative may include linking group(s) that connect the polymer or the C4-C20 alkyl to the hyaluronic acid. The platinum compound includes dichloro(1,2-diaminocyclohexane) platinum (DACHPt), cisplatin and oxaliplatin. This intralymphatic delivery method offers significant advantages for the use of platinum medicines in treating lymphatic cancer.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: April 28, 2020
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chih-Peng Liu, Ya-Chin Lo, Ming-Cheng Wei, Maggie Lu, Shuen-Hsiang Chou, Shih-Ta Chen, Hsiang-Wen Tseng
  • Patent number: 10629673
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a conductive terminal exposed from a passivation; forming a capacitor structure under the passivation proximal to a heterogeneous interface; electrically connecting the capacitor structure to the conductive terminal and isolating the capacitor structure from other electrical components in the semiconductor structure; and probing the conductive terminal to measure an electrical parameter of the capacitor structure covered by the passivation, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: April 21, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Yang-Che Chen, Chen-Hua Lin, Huang-Wen Tseng, Victor Chiang Liang, Chwen-Ming Liu
  • Publication number: 20200098851
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes: providing a conductive terminal exposed from a passivation; forming a capacitor structure under the passivation proximal to a heterogeneous interface; electrically connecting the capacitor structure to the conductive terminal and isolating the capacitor structure from other electrical components in the semiconductor structure; and probing the conductive terminal to measure an electrical parameter of the capacitor structure covered by the passivation, wherein the electrical parameter corresponds to a humidity permeability at the heterogeneous interface. A semiconductor structure thereof is also provided.
    Type: Application
    Filed: January 18, 2019
    Publication date: March 26, 2020
    Inventors: YANG-CHE CHEN, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Publication number: 20200075435
    Abstract: A semiconductor device includes a substrate including a circuit region and an outer border, a plurality of detecting devices disposed over the substrate and located between the circuit region and the outer border, first and second probe pads electrically connected to two ends of each detecting device, and a seal ring located between the outer border of the substrate and the detecting devices. A method for detecting defects in a semiconductor device includes singulating a die having a substrate, a plurality of detecting devices, a first probe pad and a second probe pad electrically connected to two ends of each detecting device, and a seal ring; probing the first and the second probe pads to determine a connection status of the detecting devices; and recognizing a defect when the connection status of the detecting devices indicates an open circuit.
    Type: Application
    Filed: January 22, 2019
    Publication date: March 5, 2020
    Inventors: YANG-CHE CHEN, WEI-YU CHOU, HONG-SENG SHUE, CHEN-HUA LIN, HUANG-WEN TSENG, VICTOR CHIANG LIANG, CHWEN-MING LIU
  • Patent number: 10580862
    Abstract: A high-voltage semiconductor device has a main high-voltage switch device and a current-sense device for mirroring the current through the main high-voltage switch device. The main high-voltage switch device has a plurality of switch cells arranged to form a first array on a semiconductor substrate. Each switch cell has a first cell width. The current-sense device has a plurality of sense cells arranged to form a second array on the semiconductor substrate. Each sense cell has a second cell width larger than the first cell width. The switch cells and the sense cells share a common gate electrode and a common drain electrode.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: March 3, 2020
    Assignee: LEADTREND TECHNOLOGY CORPORATION
    Inventors: Wan Wen Tseng, Jen-Hao Yeh, Yi-Rong Tu, Chin-Wen Hsiung
  • Publication number: 20200001022
    Abstract: The present disclosure provides improved technologies relating to medical fluid heating systems and apparatus. In certain embodiments, the present disclosure relates to systems and apparatus for heating a fluid and, more particularly, for quickly and controllably heating a flow of blood or a blood product, for example, for infusion into a patient or for hyperthermia treatment. In particular, in a first aspect, the present disclosure is directed to a system and apparatus featuring single flow path fluid heating (“single path flow”). Moreover, in a second aspect, the present disclosure is directed to a system, apparatus, and related method for efficiently utilizing the thermal energy of an infusate stored in a reservoir (“slack time heating”). Furthermore, in a third aspect, the present disclosure is directed to a fluid heating system and apparatus featuring a vacuum release valve designed to prevent the undesired orientation of deformed inflow tubing (“vacuum release valve”).
    Type: Application
    Filed: November 29, 2017
    Publication date: January 2, 2020
    Applicant: Belmont Instrument, LLC
    Inventors: John Joseph Landy, III, George G. Brusard, Tristan Dion, Yeu Wen Tseng
  • Publication number: 20190371783
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Inventors: Tseng Chin LO, Molly CHANG, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
  • Publication number: 20190333829
    Abstract: A method of detecting delamination in an integrated circuit package structure, the method includes forming a plurality of through vias over a carrier substrate; placing a device die over the carrier substrate and between the through vias, wherein the device die comprises a metal pillar; forming a molding material surrounding the device die and the through vias; forming a testing metal line extending along a top surface of the molding material and past an interface between the device die and the molding material; applying a current to the testing metal line; detecting an electrical signal of the testing metal line during the applying the current to the testing metal line; and determining, based on the detected electrical signal of the testing metal line, whether a delamination occurs between the device die and the molding material.
    Type: Application
    Filed: July 8, 2019
    Publication date: October 31, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yang-Che CHEN, Tsung-Te CHOU, Chen-Hua LIN, Huang-Wen TSENG, Chwen-Ming LIU
  • Publication number: 20190302838
    Abstract: A display device includes at least one speaker, a signal transceiver and a processor. The at least one speaker outputs a sound according to a volume parameter. The signal transceiver receives incoming call information from a communication device. The processor is electrically coupled to the at least one speaker and the signal transceiver. The processor detects signal strength of the communication device and adjusts the volume parameter according to the incoming call information and the signal strength, in order to increase or decrease a volume of the sound.
    Type: Application
    Filed: March 17, 2019
    Publication date: October 3, 2019
    Inventors: Chiung-Wen TSENG, Min-Cheng WU, Yi-Xuan HUANG