Patents by Inventor Wen Tseng

Wen Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10153290
    Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a substrate; a field effect transistor disposed in a periphery region of the substrate, the field effect transistor including a gate electrode, a first source, a first drain; a floating gate non-volatile memory device disposed in a memory region of the substrate, the floating gate non-volatile memory device including a second source, a third source, and a second drain, wherein the second source, the third source, and the second drain are disposed along an axis; and a floating gate electrode in the memory region including a first portion, a second portion, and a third portion, wherein the first portion, the second portion, and the third portion are electrically connected, wherein the first portion, the second portion and the third portion extend perpendicular to the axis.
    Type: Grant
    Filed: September 15, 2015
    Date of Patent: December 11, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Felix Ying-Kit Tsui, Huang-Wen Tseng
  • Patent number: 10137257
    Abstract: Presented herein are various systems, methods, and apparatuses for heating infusate by an induction heater e.g., an electromagnetic heater, and storing thermal energy in a reservoir of thusly heated infusate. In certain embodiments, a system includes a reservoir for containing an infusate, a fluid heater, a diversion valve, a patient line, and a recirculation line.
    Type: Grant
    Filed: November 30, 2016
    Date of Patent: November 27, 2018
    Assignee: Belmont Instrument, LLC
    Inventors: John J. Landy, III, Yeu Wen Tseng
  • Publication number: 20180323258
    Abstract: A high-voltage semiconductor device has a main high-voltage switch device and a current-sense device for mirroring the current through the main high-voltage switch device. The main high-voltage switch device has a plurality of switch cells arranged to form a first array on a semiconductor substrate. Each switch cell has a first cell width. The current-sense device has a plurality of sense cells arranged to form a second array on the semiconductor substrate. Each sense cell has a second cell width larger than the first cell width. The switch cells and the sense cells share a common gate electrode and a common drain electrode.
    Type: Application
    Filed: May 3, 2018
    Publication date: November 8, 2018
    Inventors: Wan Wen TSENG, Jen-Hao YEH, Yi-Rong TU, Chin-Wen HSIUNG
  • Publication number: 20180314356
    Abstract: The present invention relates to a method for sensing a stylus on a display device and a device for using the same. The display device has multiple sub-pixels and multiple common electrodes respectively corresponding to at least one of the sub-pixels. In the sensing stylus method, a signal of an active stylus is sensed through one of the common electrodes for displyaing an image in a displaying duration of the display device.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 1, 2018
    Applicant: ELAN MICROELECTRONICS CORPORATION
    Inventors: Jyun-Yu Chen, Hsuan-Wen Tseng, Chia-Hsing Lin
  • Patent number: 10036223
    Abstract: A method according to one or more aspects of the disclosure includes actuating a slip device to grip a tubular extending through a bore, the slip device has an upper set of slips spaced axially above a lower set of slips and the actuating includes radially moving in unison the upper and the lower sets of slips from an open position to an extended position gripping the tubular.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: July 31, 2018
    Assignee: Bastion Technologies, Inc.
    Inventors: George Fabela, Dewey Louvier, Charles Don Coppedge, Shyang Wen Tseng
  • Patent number: 10037975
    Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.
    Type: Grant
    Filed: August 11, 2017
    Date of Patent: July 31, 2018
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wei-Ming Hsieh, Yu-Pin Tsai, Man-Wen Tseng
  • Publication number: 20180204907
    Abstract: A power metal-oxide-semiconductor field-effect transistor (MOSFET) device includes a first metal layer, a substrate, an epitaxy layer, a plurality of first trench wells, a plurality of second trench wells, a plurality of body structure layers, a plurality of polysilicon layers, and a second metal layer. A part of a depletion region is formed between each first trench well and the epitaxy layer and between a body structure layer corresponding to the each first trench well and the epitaxy layer, and a rest part of the depletion region is formed between a second trench well corresponding to the each first trench well and the epitaxy layer. The plurality of second trench wells increase a breakdown voltage of the power MOSFET device and reduce a conduction resistor of the power MOSFET device.
    Type: Application
    Filed: January 11, 2018
    Publication date: July 19, 2018
    Inventors: Chih-Wen Hsiung, Jen-Hao Yeh, Yi-Rong Tu, Wan-Wen Tseng
  • Publication number: 20180156865
    Abstract: An integrated circuit package structure includes a device die having a plurality of metal pillars, a molding material directly in contact with at least one side surface of the device die, a first dielectric layer disposed on the device die and on the molding material, and a testing pad disposed in the first dielectric layer and directly in contact with an interface between the device die and the molding material. The testing pad is electrical isolated from the metal pillars.
    Type: Application
    Filed: February 22, 2017
    Publication date: June 7, 2018
    Inventors: Yang-Che Chen, Tsung-Te Chou, Chen-Hua Lin, Huang-Wen Tseng, Chwen-Ming Liu
  • Publication number: 20180143181
    Abstract: An in vitro method for screening a testing compound to evaluate its potential as a liver drug is provided. The method includes applying the testing compound to cells of an isolated human liver tumor cell line, named as ITRI-H16, measuring a cell viability of the cells and determining the effect of the testing compound on the cells by calculating a half maximal inhibitory concentration (IC50) of the testing compound.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 24, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Mei-Wei Lin, Dian-Kun Li, Ling-Mei Wang, Ching-Huai Ko, Chin-Pen Lai, Chun-Chung Wang, Hsiang-Wen Tseng
  • Publication number: 20180142214
    Abstract: An in vitro method for screening a testing compound to evaluate its potential as a liver drug of the disclosure is provided. The method includes applying the testing compound to cells of an isolated human liver tumor cell line, named as ITRI-H28, measuring a cell viability of the cells and determining the effect of the testing compound on the cells by calculating a half maximal inhibitory concentration (IC50) of the testing compound.
    Type: Application
    Filed: January 3, 2018
    Publication date: May 24, 2018
    Applicant: Industrial Technology Research Institute
    Inventors: Mei-Wei Lin, Dian-Kun Li, Ling-Mei Wang, Ching-Huai Ko, Chin-Pen Lai, Chun-Min Liu, Hsiang-Wen Tseng
  • Publication number: 20180122818
    Abstract: A memory device includes a semiconductor substrate having a cell region and a peripheral region surrounding the cell region and a pair of control gate stacks on the cell region. Each of the control gate stacks includes a storage layer and a control gate on the storage layer. The memory device includes at least one high-? metal gate stack disposed on the substrate. The high-? metal gate stack has a metal gate and a high-? dielectric film wrapping around the metal gate, and a top surface of the control gate is lower than a top surface of the metal gate.
    Type: Application
    Filed: October 31, 2016
    Publication date: May 3, 2018
    Inventors: Yu-Wen Tseng, Tsung-Yu Yang, Chung-Jen Huang
  • Publication number: 20180106299
    Abstract: According to embodiments of the present disclosure, a clutch pack is provided. The clutch pack includes a first set of clutch plates arranged in an alternating configuration with a second set of clutch plates. The first set of clutch plates has a plurality of friction pads made of friction material and defining channels in the friction material. The channels are configured to allow lubricant to flow between the friction pads. Each of the friction pads defines a groove in the friction pad. The groove is disconnected from the channels. The groove thereby creates a flow induced high pressure region forcing the first set of clutch plates to a center between the second set of clutch plates.
    Type: Application
    Filed: October 14, 2016
    Publication date: April 19, 2018
    Inventors: DENGFU ZHANG, JAU-WEN TSENG, DAVID BECK
  • Publication number: 20180061813
    Abstract: A semiconductor device package including a first encapsulation layer, a redistribution layer disposed on the first encapsulation layer, a first die disposed on the redistribution layer, a second encapsulation layer covering the first die and the redistribution layer, and an electrical connection terminal electrically connected to the redistribution layer. The first encapsulation layer has a first surface and a second surface different from the first surface. The first encapsulation layer surrounds a portion of the electrical connection terminal and exposes the electrical connection terminal.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Li-Hao LYU
  • Publication number: 20180061727
    Abstract: A semiconductor device package comprises an adhesive layer, a die on the adhesive layer, a first encapsulation layer encapsulating the die and the adhesive layer, and a second encapsulation layer adjacent to the first encapsulation layer and the adhesive layer. The second encapsulation layer has a first surface and a second surface different from the first surface. A contact angle of the first surface of the second encapsulation layer is different from a contact angle of the second surface of the second encapsulation layer.
    Type: Application
    Filed: August 11, 2017
    Publication date: March 1, 2018
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Li-Hao LYU, Chieh-Ju TSAI, Yu-Kai LIN, Wei-Ming HSIEH, Yu-Pin TSAI, Man-Wen TSENG, Yu-Ting LU
  • Publication number: 20180010988
    Abstract: The present invention provides a packaging unit for liquid sample loading devices applied in an electron microscope. The liquid sample loading devices may be easily, rapidly, precisely and stably aligned and packaged by an engagement of an upper jig and a bottom jig as well as a first fixing pillar supported in a slide track of the packaging unit. Accordingly, efficiency and a yield of packaging the liquid sample loading devices may be improved. In addition, the packaging unit for the liquid sample loading devices of the present invention may directly package a liquid sample, and thus the liquid sample may maintain its original state.
    Type: Application
    Filed: July 7, 2017
    Publication date: January 11, 2018
    Inventor: Shih-Wen TSENG
  • Publication number: 20180006010
    Abstract: Provided is a method for inserting a pre-designed filler cell, as a replacement to a standard filler cell, including identifying at least one gap among a plurality of functional cells. In some embodiments, a pre-designed filler cell is inserted within the at least one gap. By way of example, the pre-designed filler cell includes a layout design having a pattern associated with a particular failure mode. In various embodiments, a layer is patterned on a semiconductor substrate such that the pattern of the layout design is transferred to the layer on the semiconductor substrate. Thereafter, the patterned layer is inspected using an electron beam (e-beam) inspection process.
    Type: Application
    Filed: April 11, 2017
    Publication date: January 4, 2018
    Inventors: Tseng Chin LO, Molly Chang, Ya-Wen TSENG, Chih-Ting SUN, Zi-Kuan LI, Bo-Sen CHANG, Geng-He LIN
  • Publication number: 20170370424
    Abstract: A vehicle transmission includes a first rotating element, second rotating element, first retainer ring, and second retainer ring. The first rotating element has an exterior surface that defines a first ring groove. The second rotating element is configured to limit movement of friction plates during clutch engagement. The second rotating element is disposed about the exterior surface and has an interior surface that defines a second ring groove. The first retainer ring is disposed in the first ring groove. The second retainer ring is disposed in the second ring groove and thereby restricts movement of the first retainer ring in a radially outward direction.
    Type: Application
    Filed: June 28, 2016
    Publication date: December 28, 2017
    Inventors: Carl GARBACIK, Marvin YOUNG, Mark William MARCHIE, Jau-Wen TSENG, Bhupinder SINGH, Patrick DUFF
  • Patent number: 9829411
    Abstract: A bench test calibration method for generating wet clutch torque transfer functions includes obtaining in-vehicle clutch torques at a set of shift conditions; performing a series of bench tests at various clutch pack clearances and lubrication oil flow rates at the set of shift conditions; adjusting clutch pack clearances and lubrication oil flow rates during the series of bench tests in response to a difference between a bench test measured clutch torques and the corresponding in-vehicle clutch torques exceeding a threshold; and recording relationships between first bench test measured torques and force profiles of a clutch actuator relative to the adjusted clutch pack clearances and lubrication oil flow rates for each of the set of shift conditions as a first transfer function.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: November 28, 2017
    Assignee: Ford Global Technologies, LLC
    Inventors: Yuji Fujii, Gregory Michael Pietron, Diana Yanakiev, Eric Hongtei Tseng, Vladimir Ivanovic, Jau-Wen Tseng
  • Publication number: 20170234095
    Abstract: A method according to one or more aspects of the disclosure includes actuating a slip device to grip a tubular extending through a bore, the slip device has an upper set of slips spaced axially above a lower set of slips and the actuating includes radially moving in unison the upper and the lower sets of slips from an open position to an extended position gripping the tubular.
    Type: Application
    Filed: February 3, 2016
    Publication date: August 17, 2017
    Inventors: George Fabela, Dewey Louvier, Charles Don Coppedge, Shyang Wen Tseng
  • Patent number: 9682062
    Abstract: The disclosure provides a pharmaceutical composition for inhibiting angiogenesis, including an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient. The pharmaceutical composition may further include a pharmaceutically acceptable carrier or salt. The disclosure also provides a method for inhibiting angiogenesis, including administering an effective amount of an extract of Juniperus chinensis or an effective amount of a lignan as an effective ingredient for inhibiting angiogenesis to a subject in need thereof.
    Type: Grant
    Filed: December 18, 2013
    Date of Patent: June 20, 2017
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: I-Horng Pan, Hsin-Jan Yao, Mei-Wei Lin, I-Huang Lu, Hsin-Chieh Wu, Hsiang-Wen Tseng, Ching-Huai Ko, Chun-Chung Wang, Zong-Keng Kuo, Shyh-Horng Lin, Yi-Cheng Cheng, Tien-Soung Tong