Abstract: A semiconductor device includes a post-passivation interconnect (PPI) structure having a landing pad region. A polymer layer is formed on the PPI structure and patterned with a first opening and a second opening to expose portions of the landing pad region. The second opening is a ring-shaped opening surrounding the first opening. A bump structure is formed on the polymer layer to electrically connect the landing pad region through the first opening and the second opening.

Abstract: A touch system using processor to configure touch detection architecture, including: a sensor unit having a plurality of sensors; a connection unit for determining a sensors joined configuration of the plurality of sensors according to at least one connection control signal; a touch scan unit for coupling at least one touch signal to the connection unit according to at least one scan configuration signal; a touch detection unit for outputting the touch signal and deriving touch information from a parameter of the touch signal according to at least one operation mode configuration signal; and a processor unit for outputting the at least one connection control signal, the scan configuration signal, and the operation mode configuration signal according to a content of a control table, and receiving the touch information.

Abstract: Methods and apparatuses for wafer level packaging (WLP) of semiconductor devices are disclosed. A contact pad of a circuit may be connected to a solder bump by way of a post passivation interconnect (PPI) line and a PPI pad. The PPI pad may comprise a hollow part and an opening. The PPI pad may be formed together with the PPI line as one piece. The hollow part of the PPI pad can function to control the amount of solder flux used in the ball mounting process so that any extra amount of solder flux can escape from an opening of the solid part of the PPI pad. A solder ball can be mounted to the PPI pad directly without using any under bump metal (UBM) as a normal WLP package would need.

Abstract: A multi-band antenna includes a conductive cap, a ground plane element, a supporting frame, a first radiating conductive element, a second radiating conductive element, a third radiating conductive element, and a plurality of conductive pieces. The multi-band antenna of the disclosure makes the radiating conductive element contact with the conductive cap physically via the conductive piece. Therefore, although a gap similar to a slot is formed, the resonant mode of the multi-band antenna is not excited via the slot.

Abstract: Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.

Abstract: A via or pillar structure, and a method of forming, is provided. In an embodiment, a polymer layer is formed having openings exposing portions of an underlying conductive pad. A conductive layer is formed over the polymer layer, filling the openings. The dies are covered with a molding material and a planarization process is performed to form pillars in the openings. In another embodiment, pillars are formed and then a polymer layer is formed over the pillars. The dies are covered with a molding material and a planarization process is performed to expose the pillars. In yet another embodiment, pillars are formed and a molding material is formed directly over the pillars. A planarization process is performed to expose the pillars. In still yet another embodiment, bumps are formed and a molding material is formed directly over the bumps. A planarization process is performed to expose the bumps.

Abstract: A production performance management device and a production performance management method thereof are provided. The production performance management device includes a connection interface, a storage and a processor. The connection interface receives production data. The storage stores the production data and a production performance management program. The processor runs the production performance management program. The production performance management program defines a main objective, a plurality of measurement indices, a plurality of factors, a custom mapping function between the main objective and the measurement indices and a plurality of specific mapping functions between the measurement indices and the factors, and uses the custom mapping function and the specific mapping functions to decide a factor value of each of the factors from the production data to make a main objective value of the main objective meet a main constraint.

Abstract: The present invention is related to an UV LED curing apparatus, and more particularly, to an UV LED curing apparatus with improved housing and switch controller. The light reflective inner casing is preferably provided as an effective UV light reflector and as a supporting substrate of the UV LED light source while being capable of transmitting heat from the UV LED light source away for further heat dissipation to the ambient by the outer casing. The outer casing is detachably attached to the inner casing and allows a greater user interaction for decorative and entertainment purposes while also being a protective and heat dissipation means.

Abstract: Integrated circuits with clocked storage elements are provided. A clocked storage element such as a flip-flop circuit may include a master latch, a slave latch, and associated control circuitry. The master and slave latches may be implemented using dual-interlocked cell (DICE) latch configurations. The DICE latch may include at least four inverting circuits having two redundant node pairs and may exhibit immunity to soft error upset (SEU) events. Each of the master and slave latches may be separated into different portions so that the redundant nodes are physically separated by interposing circuitry. The redundant nodes may also be formed in separate wells to further minimize charge sharing. The different portions of the master and slave latch may be interleaved to minimize area.

Abstract: A photoelectric coupling module includes a substrate, a photoelectric unit, and a lens module. The substrate carries at least two alignment marks for correct and absolute positioning of the lens module on the substrate. The photoelectric unit is positioned on the substrate. The lens module defines at least two through holes aligned with the alignment marks.

Abstract: The present invention relates generally to methods of treating cancer with arginine deiminase, and in particular pegylated arginine deiminase.

Abstract: An electronic paper touch device including: a first substrate; a first electrode layer located on the first substrate; an electronic paper display layer located on the first electrode layer; a transparent electrode layer located on the electronic paper display layer and having plural transparent electrodes; a second substrate located on the transparent electrode layer; and a control unit having a touch mode and an electronic paper mode, wherein, when the control unit is in the touch mode, the control unit will couple a touch detection unit with the first electrode layer and with the transparent electrode layer to perform a capacitive touch detection procedure.

Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a first active region adjacent a first side of a shallow trench isolation (STI) region. The first active region including a first proximal fin having a first proximal fin height adjacent the STI region, and a first distal fin having a first distal fin height adjacent the first proximal fin, the first proximal fin height less than the first distal fin height. The STI region includes oxide, the oxide having an oxide volume, where the oxide volume is inversely proportional to the first proximal fin height. A method of formation includes forming a first proximal fin with a first proximal fin height less than a first distal fin height of a first distal fin, such that the first proximal fin is situated between the first distal fin and an STI region.

Abstract: The present disclosure is directed to a semiconductor structure and a method of manufacturing a semiconductor structure in which a spacer element is formed adjacent to a metal body embedded in a first dielectric layer of a first interconnect layer. A via which is misaligned relative to an edge of the metal body is formed in a second dielectric material in second interconnect layer disposed over the first interconnect layer and filled with a conductive material which is electrically coupled to the metal body. The method allows for formation of an interconnect structure without encountering the various problems presented by via substructure defects in the dielectric material of the first interconnect layer, as well as eliminating conventional gap-fill metallization issues.

Abstract: A semiconductor device including a dielectric layer formed on the surface of a post-passivation interconnect (PPI) structures. A polymer layer is formed on the dielectric layer and patterned with an opening to expose a portion of the dielectric layer. The exposed portion of the dielectric layer is then removed to expose a portion of the PPI structure. A solder bump is then formed over and electrically connected to the first portion of the PPI structure.

Abstract: A lighting device controllable by hover operation, including: a shell body; a light source unit; at least one conductive sensor; and a circuit board, which includes a capacitive touch detection circuit, a light source driver circuit, and a control unit; wherein, when a finger or a palm of an operator approaches at least one active region of the shell body during a control operation, each of the at least one active region being opposing one of the at least one conductive sensor, the capacitive touch detection circuit will detect a capacitance change signal via the at least one conductive sensor and generate an operation signal accordingly, and the control unit will control the light source driver circuit in response to the operation signal to determine a light emitting status of the light source unit.

Abstract: An isolated Clostridium cadaveris ITRI04005 and its uses are provided. The isolated Clostridium cadaveris ITRI04005 was deposited at German Collection of Microorganisms and Cell Cultures (Deutsche Sammlung von Mikroorganismen and Zellkulturen GmbH, DSMZ) under the accession number DSM 32078.

Abstract: A power-saving remote control apparatus (40) includes a remote control receiving unit (1022) and a main control unit (104). The main control unit (104) is configured to control the power-saving remote control apparatus (40) to enter a working mode when a controlled apparatus (30) needs to be turned on. The main control unit (104) is configured to control the power-saving remote control apparatus (40) to enter a sleeping-power-saving mode when the controlled apparatus (30) stops working, and then for every first predetermined time, the main control unit (104) is turned on to wake up the remote control receiving unit (1022) to scan a plurality of wireless signals (52). The main control unit (104) is configured to control the power-saving remote control apparatus (40) to enter the working mode if the wireless signals (52) include a wireless starting signal (54) for starting the controlled apparatus (30).

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first dielectric layer disposed over the substrate and a metal structure disposed in the first dielectric layer and below a surface of the first dielectric layer. The metal structure has a such shape that having an upper portion with a first width and a lower portion with a second width. The second width is substantially larger than the first width. The semiconductor device also includes a sub-structure of a second dielectric positioned between the upper portion of the metal structure and the first dielectric layer.

Abstract: A method of making a semiconductor device includes forming an under bump metallurgy (UBM) layer over a substrate, the UBM layer comprising sidewalls and a surface region. The method further includes forming a conductive pillar over the UBM layer, the conductive pillar includes sidewalls, wherein the conductive pillar exposes the surface region of the UBM layer. The method further includes forming a non-metal protective structure over the sidewalls of the conductive pillar, wherein the non-metal protective structure contacts the surface region of the UBM layer, and the non-metal protective structure exposes the sidewalls of the UBM layer.