Abstract: A projection apparatus includes an image projection module, a lens module and a light emitting module. The image projection module has a first optical axis and forms a projection area on a bearing surface. A projection of the first optical axis on an X-Z plane is perpendicular to an X-Y plane on which the projection area is formed. The lens module comprises N cameras, each having a corresponding second optical axis and being for forming a shooting area. The N second axes are tilted to the first optical axis and have an angle with respect to the X-Z plane. The light emitting module includes M light emitting components, each having a corresponding third optical axis and being for forming a sensing area. The projection area, the N shooting areas and the M sensing areas are at least partially overlapped with each other to form a rectangular shooting sensing area.

Abstract: A computer system having a sensing function includes a base, a first light emitting assembly and a second light emitting assembly. The base is disposed on a bearing surface. The first light emitting assembly is disposed in the base and has a first optical axis. The second light emitting assembly is disposed in the base and has a second optical axis. A distance between the firs optical axis and the second optical axis is D. An inner edge of a first light source emitted by the first light emitting assembly and an inner edge of a second light source emitted by the second light emitting assembly intersect at a point on the bearing surface, thereby forming an irregular-shaped sensing region having a boundary passing through the point. A length of a shortest side of the irregular-shaped sensing region is less than or equal to 2D.

Abstract: A projection device includes a projection module and a first camera module. The projection device has a first optical axis and configured to form a projection area, wherein a projection of the first optical axis on an X-Z plane of the projection device is perpendicular to an X-Y plane on which the projection area is formed. The first camera module is disposed on a side of the projection module and includes a second optical axis, wherein the first camera module is configured to form a first shooting area, the second optical axis forms a first angle ??1 with respect to the first optical axis, the projection area at least partially overlaps the first shooting area to form an overlapping area, and the first angle ??1 is a function of a distance between the projection module and the first camera module.

Abstract: A method of protecting a serializer/deserializer (SERDES) differential input/output (I/O) circuit includes detecting an electrostatic discharge event. The method also includes selectively disengaging a power supply terminal from a pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event. The method further includes selectively disengaging a ground terminal from the pair of I/O transistors of the SERDES differential I/O circuit in response to the detected electrostatic discharge event.

Abstract: A multiple lens system includes at least one lens unit, at least one reflecting unit, a first image sensing element, a second image sensing element, and a processing unit. The processing unit is electrically connected to the first image sensing element and the second image sensing element. The processing unit controls at least one angle of the at least one reflection unit according to a capturing mode, changes at least one optical path of the at least one reflection unit, and selects at least one lens of the at least one lens unit. At least one image beam obtained by the selected at least one lens is reflected or projected to at least one of the first image sensing element and the second image sensing element through the at least one optical path.

Abstract: The present invention provides a method for labeling or detecting a protein with certain glycosyl groups. The methods are particularly useful for detecting cancer cells comprising the detected glycosyl groups. The present invention further provides labeling agents and detection agents, labeled proteins and mixtures, and kits and arrays thereof.

Abstract: A method for fabricating a multi-layer, crown-shaped MIM capacitor is provided. A base having therein a conductive region within a capacitor-forming region is formed. An IMD layer is deposited on the base to cover the capacitor-forming region. A capacitor trench is formed within the capacitor-forming region. The capacitor trench penetrates through the IMD layer, thereby exposing a portion of the conductive region. A concentric capacitor lower electrode structure is formed within the capacitor trench. The concentric capacitor lower electrode structure includes a first electrode and a second electrode surrounded by the first electrode. The first electrode is in direct contact with the conductive region. A conductive supporting pedestal is formed within the capacitor trench for fixing and electrically connecting bottom portions of the first and second electrodes. A capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal is formed.

Abstract: A semiconductor package includes a cover, a substrate, at least one semiconductor device and at least one corner stiffener. The cover has at least one corner portion. The substrate is in force communication with the cover. The substrate has at least one corner portion. The semiconductor device is present between the cover and the substrate. The corner stiffener is present on at least one of the corner portion of the cover and the corner portion of the substrate.

Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

Abstract: A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units.

Abstract: An electrical connector includes an insulative housing, a positive terminal received in the housing and a metallic shell shielding around the mating portion. The housing has a base portion and a mating portion extending forwardly from the base portion. The metallic shell shields around the mating portion to form a first mating cavity opening forwardly and surrounding an outer surface of the mating portion. The mating portion has a second mating cavity recessed from a front face thereof to be separated from the first mating cavity and opening forwardly. The positive terminal has a contacting portion exposed in the second mating cavity. The metallic shell has at least one elastic pressing portion extending into the first mating cavity to be used as a negative terminal.

Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.

Abstract: A reference voltage circuit is provided, which includes bandgap reference circuit, bias current generator, first capacitor, second capacitor, comparator and control logic circuit. In the active mode of the control logic circuit, the control logic circuit controls the bandgap reference circuit to deliver bandgap reference voltage. The comparator transmits first comparison signal to control logic circuit when the first and second capacitors are charged to the bandgap reference voltage. The control logic circuit enters low power mode and controls the bandgap reference circuit to stop delivering the bandgap reference voltage. If the comparator detects the potential difference between the first capacitor and second capacitor exceeds the threshold value, the control logic circuit returns to active mode according to the second comparison signal transmitted form the comparator.

Abstract: An electrical connector includes an insulative seat, a plurality of terminals fixed to the insulative seat and at least one magnetic element retained in the insulative seat. The insulative seat defines a vertical first mating surface and a mating portion extending forwardly from the first mating surface, the mating portion defines an inclined second mating surface. Each terminal defines a contacting portion disposed in the mating portion and a soldering portion extending outside of the insulative seat. The mating portion defines a shallow recess recessed from the second mating surface, and the contacting portion defines a free end exposed on the shallow recess and locating behind the second mating surface.

Abstract: A voltage generating circuit comprising: a first switch circuit, operating in a first power domain; a second switch circuit, operating in a second power domain; a first transistor of first type, comprising a control terminal coupled to the first switch circuit and the second first switch circuit, wherein the control terminal of the first transistor of first type is coupled to a predetermined voltage source via the first switch circuit if the first switch circuit is active, wherein the control terminal of the first transistor of first type is coupled to the predetermined voltage source via the second switch circuit if the second switch circuit is active; and an output circuit, coupled to the first transistor of first type and operating in the second power domain.

Abstract: The present invention relates to methods of treating cancer, suppressing or inhibiting tumorigenesis, tumor growth or cancer progression, and suppressing or inhibiting cancer cells from altering cellular metabolism in favor of cancerous growth. Also provided are compositions comprising an agent that decreases glycosylation of phosphofructokinase 1 or increases phosphofructokinase 1 expression or activity.

Abstract: A method to make dyed functional film comprising the steps of providing a soluble polymer material; adding an appropriate solvent to the polymer material to make a soluble polymer solution; providing a soluble dye; adding an appropriate solvent to the dye to make a soluble dye solution; adding the dye solution to the polymer or PVA solution, and introducing the dyed polymer or PVA solution to a solution casting device; removing a thin dyed functional film from the casting device; and letting the dyed functional film dry and solidified.

Abstract: A multi-layer, crown-shaped MIM capacitor includes a base having therein conductive region, an inter-metal dielectric (IMD) layer on the base, a capacitor trench penetrating through the IMD layer and exposing the conductive region, a capacitor lower electrode structure including a first electrode and a second electrode surrounded by the first electrode, a conductive supporting pedestal within the capacitor trench for fixing and electrically connecting the bottom portions of the first and second electrodes, a capacitor dielectric layer conformally lining the first and second electrodes and a top surface of the conductive supporting pedestal, and a capacitor upper electrode on the capacitor dielectric layer.

Abstract: A display panel, including a device substrate, an opposite substrate, a sealant, and a display medium, is provided. A pixel array of the device substrate is located in a display region, and a periphery circuit of the device substrate is located in a non-display region, wherein the periphery circuit includes at least one driving device, a planarization layer, and at least one wire. The planarization layer covers the driving device. The wire is located on the planarization layer, and the wire is electrically connected with the driving device and disposed to overlap the driving device. The opposite substrate is located opposite to the device substrate, and the sealant is located in the non-display region therebetween and covers the wire. The display medium is located between the device substrate, the opposite substrate, and the sealant. A manufacturing method of a display panel is also provided.

Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.