Patents by Inventor Wen Yi

Wen Yi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Package on Packaging Structure and Methods of Making Same
    Publication number: 20150200190
    Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.
    Type: Application
    Filed: January 8, 2015
    Publication date: July 16, 2015
    Inventors: Wen-Yi Lin, Jiun Yi Wu, Jing Ruei Lu, Po-Yao Lin, Ming-Chih Yew
  • THERMALLY ENHANCED HEAT SPREADER
    Publication number: 20150179617
    Abstract: A three dimensional integrated circuit (3DIC) includes a first substrate and a heat spreading structure embedded in the first substrate. The 3DIC further includes a die electrically connected to the first substrate, wherein the die is thermally connected to the heat spreading structure. The 3DIC further includes a plurality of memory units on the die, wherein the die is between the plurality of memory units and the first substrate, and the plurality of memory units is thermally connected to the heat spreading structure by the die. The 3DIC further includes an external cooling unit on the plurality of memory units, wherein the plurality of memory units is between the die and the external cooling unit, and the die is thermally connected to the external cooling unit by the plurality of memory units.
    Type: Application
    Filed: March 3, 2015
    Publication date: June 25, 2015
    Inventors: Po-Yao LIN, Wen-Yi LIN, Shyue Ter LEU, Ming-Chih YEW
  • Semiconductor dies having substrate shunts and related fabrication methods
    Patent number: 9054155
    Abstract: Die structures for electronic device packages and related fabrication methods are provided. An exemplary die structure includes a substrate having a first layer of semiconductor material including a semiconductor device formed thereon, a handle layer of semiconductor material, and a buried layer of dielectric material between the handle layer and the first layer. The die structure also includes a plurality of shunting regions in the first layer of semiconductor material, wherein each shunting region includes a doped region in the first layer that is electrically connected to the handle layer of semiconductor material, and a body region underlying the doped region that is contiguous with at least a portion of the first layer underlying a semiconductor device.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: June 9, 2015
    Assignee: FREESCALE SEMICONDUCTOR INC.
    Inventors: Chai Ean Gill, Wen-Yi Chen
  • Antenna module
    Patent number: 9054420
    Abstract: An antenna module is provided. The antenna module includes a first ground element, a body, a radiator and a parasitic element. The body is electrically connected to the first ground element. The radiator is connected to the body, wherein the radiator includes an extending portion, a bending portion and a terminal portion, and the bending portion is connected to the extending portion, and the terminal portion is connected to the bending portion. The parasitic element includes a parasitic extending portion and a parasitic conductive portion, wherein the parasitic extending portion is connected to the parasitic conductive portion, and the terminal portion and the parasitic extending portion is located on a same straight line, and the terminal portion is separated from the parasitic extending portion.
    Type: Grant
    Filed: December 13, 2012
    Date of Patent: June 9, 2015
    Assignee: Wistron Corp.
    Inventors: Kuan-Jen Chung, Wen-Yi Tsai, Chia-Wei Su
  • LATERAL DOUBLE DIFFUSED METAL OXIDE SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20150137232
    Abstract: The present invention discloses a lateral double diffused metal oxide semiconductor (LDMOS) device and a manufacturing method thereof. The LDMOS device includes: drift region, an isolation oxide region, a first oxide region, a second oxide region, a gate, a body region, a source, and a drain. The isolation oxide region, the first oxide region, and the second oxide region have an isolation thickness, a first thickness, and a second thickness respectively, wherein the second thickness is less than the first thickness. The present invention can reduce a conduction resistance without decreasing a breakdown voltage of the LDMOS device by the first oxidation region and the second oxidation region.
    Type: Application
    Filed: October 9, 2014
    Publication date: May 21, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Ching-Yao Yang, Wen-Yi Liao, Hung-Der Su, Kuo-Cheng Chang
  • Semiconductor Device Package and Method
    Publication number: 20150123257
    Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.
    Type: Application
    Filed: January 12, 2015
    Publication date: May 7, 2015
    Inventors: Wen-Yi Lin, Kuo-Chuan Liu, Po-Yao Lin, Cheng-Yi Hong, Ming-Chih Yew
  • Brake distribution structure
    Patent number: 9004234
    Abstract: Provided is a brake distribution structure including a first sliding block, a second sliding block, and a tube. The first sliding block connects to a rear brake line of a bicycle. The second sliding block connects to a front brake line of the bicycle. The first sliding block moves to brake a rear wheel of the bicycle, and then the first sliding block drives the second sliding block to move and thereby brake the front wheel of the bicycle. The brake distribution structure ensures that the rear wheel is always braked first, prevents brake lockup, reduces hazards otherwise arising from manmade false action, and maximizes rider safety.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: April 14, 2015
    Assignee: Paul Hsu Senior High School
    Inventors: Chen-Hua Chang, Wen-Yi Huang, Chih-Po Wu, Fu-Yu You, Wen-Hsien Lin
  • Method and apparatus for making retarder in stereoscopic glasses
    Patent number: 9005493
    Abstract: A 3-d stereoscopic viewing lens which the retarder film is made of a PVA film. A 3-D stereoscopic viewing lens having a linear polarized film, one or more lens substrate layers, and an epoxy layer. A process of making retarder film including mounting a PVA film to an assembly line; wetting, cleaning, and washing the PVA film through said assembly line; softening, expanding and stretching the PVA film's x-axis through said assembly line; adding gap filling agent to the PVA film; stretching the PVA film's y-axis through a width frame holder and as a result transforming the PVA film into a retarder film.
    Type: Grant
    Filed: February 9, 2011
    Date of Patent: April 14, 2015
    Inventor: Roger Wen-Yi Hsu
  • METHOD OF FABRICATION TRANSISTOR WITH NON-UNIFORM STRESS LAYER WITH STRESS CONCENTRATED REGIONS
    Publication number: 20150087126
    Abstract: A method of fabrication a transistor device with a non-uniform stress layer including the following processes. First, a semiconductor substrate having a first transistor region is provided. A low temperature deposition process is carried out to form a first tensile stress layer on a transistor within the first transistor region, wherein a temperature of the low temperature deposition process is lower than 300 degree Celsius (° C.) . Then, a high temperature annealing process is performed, wherein a temperature of the high temperature annealing process is at least 150° C. higher than a temperature of the low temperature deposition process. Finally, a second tensile stress layer is formed on the first tensile stress layer, wherein the first tensile stress layer has a tensile stress lower than a tensile stress of the second tensile stress layer.
    Type: Application
    Filed: December 2, 2014
    Publication date: March 26, 2015
    Inventors: Chih-Chien Liu, Tzu-Chin Wu, Yu-Shu Lin, Jei-Ming Chen, Wen-Yi Teng
  • Lid design for reliability enhancement in flip chip package
    Patent number: 8976529
    Abstract: In a package structure, a stiffener ring is over and bonded to a top surface of a first package component. A second package component is over and bonded to the top surface of the first package component, and is encircled by the stiffener ring. A metal lid is over and bonded to the stiffener ring. The metal lid has a through-opening.
    Type: Grant
    Filed: January 14, 2011
    Date of Patent: March 10, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Po-Yao Lin, Tsung-Shu Lin, Kuo-Chin Chang, Shou-Yi Wang
  • Thermally enhanced heat spreader for flip chip packaging
    Patent number: 8970029
    Abstract: A flip chip microelectronic package having a heat spreader is provided. In one embodiment, the microelectronic package comprises a die having a first surface and a second surface, the first surface being coupled to a substrate; a thermal interface material disposed in thermal conductive contact with the second surface of the die; and a heat spreader adapted for dissipating heat from the die, the heat spreader disposed in thermal conductive contact with the thermal interface material. The heat spreader includes a lid having an inner chamber therein defined by a first wall and a second wall, the second wall securely joined to the first wall to seal the chamber, the lid being mounted to the substrate and a wick layer positioned in the chamber.
    Type: Grant
    Filed: May 19, 2010
    Date of Patent: March 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Yao Lin, Wen-Yi Lin
  • Electrostatic Discharge Protection Device and Manufacturing Method Thereof
    Publication number: 20150054070
    Abstract: The present invention discloses an electrostatic discharge (ESD) protection device and a manufacturing method thereof. The ESD protection device includes: a P-type well, a gate structure, an N-type source, an N-type drain, and a P-type lightly doped drain. The P-type lightly doped drain is formed in the P-type well, and at least part of the P-type lightly doped drain is beneath a spacer of the gate structure to reduce a trigger voltage of the electrostatic discharge protection device.
    Type: Application
    Filed: August 23, 2013
    Publication date: February 26, 2015
    Applicant: RICHTEK TECHNOLOGY CORPORATION
    Inventors: Tsung-Yi Huang, Wen-Yi Liao
  • 18F-labeled monomeric galactose derivative used as tomography probe
    Patent number: 8961931
    Abstract: A 18F-labeled monomeric galactose derivative is provided as a tomography probe. The derivative is a positron emission tomography (PET) probe. The derivative has high affinity and good stability in animal's body. The derivative can be an alternative glucose metabolism imaging agent used in clinic examination and quantification.
    Type: Grant
    Filed: April 7, 2011
    Date of Patent: February 24, 2015
    Assignee: Institute of Nuclear Energy Research, Atomic Energy Council
    Inventors: Ting-Shien Duh, Wuu-Jyh Lin, Jenn-Tzong Chen, Li-Yuan Huang, Hsin-Ell Wang, Chuan-Lin Chen, Wen-Yi Chang, Hao-Wen Kao
  • SPATIAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME
    Publication number: 20150048486
    Abstract: A method of fabricating a spatial semiconductor structure includes steps as follows. Firstly, a semiconductor substrate is provided. Then, a first mask layer is formed above the semiconductor substrate. Then, at least a first opening is formed in the first mask layer and exposes a portion of a surface of the semiconductor substrate. Then, a first semiconductor pattern is formed in the first opening. Then, a second mask layer is formed over the first semiconductor pattern and the first mask layer. Then, at least a second opening is formed through the second mask layer to the first mask layer and exposes another portion of the surface of the semiconductor substrate. And, a second semiconductor pattern is formed in the second opening.
    Type: Application
    Filed: August 15, 2013
    Publication date: February 19, 2015
    Applicant: UNITED MICROELECTRONICS CORPORATION
    Inventors: Hung-Lin Shih, Chih-Chien Liu, Jei-Ming Chen, Wen-Yi Teng, Chieh-Wen Lo
  • 3D Packages and Methods for Forming the Same
    Publication number: 20150041987
    Abstract: Embodiments of the present disclosure include a semiconductor device, a package and methods of forming a semiconductor device and a package. An embodiment is a semiconductor device including a molding material over a first substrate with a first opening having a first width in the molding material. The semiconductor device further includes a second opening having a second width in the molding material with the second width being greater than the first width. A first connector is in the first opening and a second connector is in the second opening.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 12, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Chih Yew, Wen-Yi Lin, Fu-Jen Li, Po-Yao Lin, Kuo-Chuan Liu
  • Package on packaging structure and methods of making same
    Patent number: 8946888
    Abstract: A package on packaging structure provides for improved thermal conduction and mechanical strength by the introduction of a sold thermal coupler between the first and second packages. The first package has a first substrate and through vias through the first substrate. A first set of conductive elements is aligned with and coupled to the through vias of the first substrate. A solid thermal coupler is coupled to the first set of conductive elements and to a die of the second package. A second set of conductive elements is coupled to the die and a bottom substrate is coupled to the second set of conductive elements. The thermal coupler may be, e.g., an interposer, a heat spreader, or a thermal conductive layer.
    Type: Grant
    Filed: September 30, 2011
    Date of Patent: February 3, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Ming-Chih Yew, Po-Yao Lin, Jing Ruei Lu, Jiun Yi Wu
  • METHOD AND SYSTEM FOR ON-LINE REAL-TIME MEASURING THE SURFACE TOPOGRAPHY AND OUT-OF-PLANE DEFORMATION BY USING PHASE-SHIFTING SHADOW MOIRE METHOD
    Publication number: 20150029514
    Abstract: The present invention is directed to a system and method for on-line real-time measuring the surface topography and out-of-plane deformation by using phase-shifting shadow moiré method. Digital Phase-Shifting Shadow Moiré Method is applied to a system, which receives the reflected images from the surface of transparent or non-transparent plate projected under a light beam passing through a grating. Next, by image correction program, the skewed interference fringe pattern is recovered to the image as if the image acquisition equipment is placed normal to the surface. Furthermore, the received images are processed with Phase-Shifting to show the surface topography of the plate.
    Type: Application
    Filed: October 29, 2013
    Publication date: January 29, 2015
    Applicant: NATIONAL TSING HUA UNIVERSITY
    Inventors: Wei-Chung WANG, Wen-Yi KANG, Ya-Hsin CHANG, Hsuan-Hao HSU
  • Semiconductor device package and method
    Patent number: 8941248
    Abstract: Various packages and methods of forming packages are disclosed. In an embodiment, a package includes a hybrid encapsulant encapsulating a chip attached to a substrate. The hybrid encapsulant comprises a first molding compound and a second molding compound that has a different composition than the first molding compound. In another embodiment, a package includes an encapsulant encapsulating a chip attached to a substrate. A surface of the chip is exposed through the encapsulant. The encapsulant comprises a recess in a surface of a first molding compound proximate the surface of the chip. A thermal interface material is on the surface of the chip and in the recess, and a lid is attached to the thermal interface material.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: January 27, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Ming-Chih Yew, Cheng-Yi Hong, Po-Yao Lin, Kuo-Chuan Liu
  • POLYSILICON LAYER
    Publication number: 20150021776
    Abstract: A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.
    Type: Application
    Filed: October 6, 2014
    Publication date: January 22, 2015
    Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen, Wen-Yi Teng, Chan-Lon Yang
  • PROTECTION DEVICE AND RELATED FABRICATION METHODS
    Publication number: 20150021739
    Abstract: Protection device structures and related fabrication methods are provided. An exemplary semiconductor protection device includes a base region of semiconductor material having a first conductivity type, an emitter region within the base region having the opposite conductivity type, and a collector region of semiconductor material having the second conductivity type, wherein at least a portion of the base region resides between the emitter region and the collector region. A depth of the collector region is greater than a depth of the emitter region and less than or equal to a depth of the base region such that a distance between a lateral boundary of the emitter region and a proximal lateral boundary of the collector region is greater than zero and the collector region does not overlap or otherwise underlie the emitter region.
    Type: Application
    Filed: July 19, 2013
    Publication date: January 22, 2015
    Inventors: WEN-YI CHEN, CHAI EAN GILL